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| 型號： | LPC3250FET296,551 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 25/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM9 MCU 256K 296-TFBGA |
| 特色產(chǎn)品： | LPC32x0 ARM926EJ-S Processor |
| 標準包裝： | 126 |
| 系列： | LPC3200 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 266MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，I²S，LCD，電機控制 PWM，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 256K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 0.9 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 296-TFBGA |
| 包裝： | 托盤 |
| 配用： | 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250 568-4742-ND - MODULE DIMM LPC2478 ARM7 622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250 |
| 其它名稱： | 568-4533 935287084551 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
31 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU. The Ethernet DMA can
access off-chip memory via the EMC, as well as the IRAM. The Ethernet block interfaces
between an off-chip Ethernet PHY using the Media Independent Interface (MII) or
Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management
(MIIM) serial bus.
7.6.2.1
Features
Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
pressure.
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
Memory management:
– Independent transmit and receive buffers memory mapped to SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
Redundancy Check (CRC) for transmit.
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching. Wake-on-LAN power
management support allows system wake-up using the receive filters or a magic
frame detection filter.
Physical interface
– Attachment of external PHY chip through standard MII or RMII interface.
– PHY register access is available via the MIIM interface.
7.6.3 USB interface
The LPC3220/30/40/50 supports USB in either device, host, or OTG configuration.
7.6.3.1
USB device controller
The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of register interface, serial interface engine, endpoint buffer memory and DMA
controller. The serial interface engine decodes the USB data stream and writes data to the
appropriate end point buffer memory. The status of a completed USB transfer or error
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