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| 型號： | LPC3250FET296,551 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 28/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM9 MCU 256K 296-TFBGA |
| 特色產(chǎn)品： | LPC32x0 ARM926EJ-S Processor |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 系列： | LPC3200 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 266MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，I²S，LCD，電機(jī)控制 PWM，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 256K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 0.9 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 296-TFBGA |
| 包裝： | 托盤 |
| 配用： | 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250 568-4742-ND - MODULE DIMM LPC2478 ARM7 622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250 |
| 其它名稱： | 568-4533 935287084551 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
34 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.7 System functions
To enhance the performance of the LPC3220/30/40/50 incorporates the following system
functions, an Interrupt Controller (INTC), a watchdog timer, a millisecond timer, and
several power control features. These functions are described in the following sections
7.7.1 Interrupt controller
The interrupt controller is comprised of three basic interrupt controller blocks, supporting a
total of 73 interrupt sources. Each interrupt source can be individually enabled/disabled
and configured for high or low level triggering, or rising or falling edge triggering. Each
interrupt may also be steered to either the FIQ or IRQ input of the ARM9. Raw interrupt
status and masked interrupt status registers allow versatile condition evaluation. In
addition to peripheral functions, each of the six general purpose input/output pins and
12 of the 22 general purpose input pins are connected directly to the interrupt controller.
7.7.2 Watchdog timer
The watchdog timer block is clocked by the main peripheral clock, which clocks a 32-bit
counter. A match register is compared to the Timer. When configured for watchdog
functionality, a match drives the match output low. The match output is gated with an
enable signal that gives the opportunity to generate two type of reset signal: one that only
resets chip internally, and another that goes through a programmable pulse generator
before it goes to the external pin RESOUT and to the internal chip reset.
7.7.2.1
Features
Programmable 32-bit timer.
Internally resets the device if not periodically reloaded.
Flag to indicate that a watchdog reset has occurred.
Programmable watchdog pulse output on RESOUT pin.
Can be used as a standard timer if watchdog is not used.
Pause control to stop counting when core is in debug state.
7.7.3 Millisecond timer
The millisecond timer is clocked by 32 kHz RTC clock, so a prescaler is not needed to
obtain a lower count rate.
The millisecond timer includes three match registers that are compared to the
Timer/Counter value. A match can generate an interrupt and the cause the Timer/Counter
either continue to run, stop, or be reset.
7.7.3.1
Features
32-bit Timer/Counter, running from the 32 kHz RTC clock.
Counter or Timer operation.
Three 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Pause control to stop counting when core is in debug state.
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