參數(shù)資料
型號: LPC3250FET296,551
廠商: NXP Semiconductors
文件頁數(shù): 50/57頁
文件大?。?/td> 0K
描述: IC ARM9 MCU 256K 296-TFBGA
特色產(chǎn)品: LPC32x0 ARM926EJ-S Processor
標(biāo)準(zhǔn)包裝: 126
系列: LPC3200
核心處理器: ARM9
芯體尺寸: 16/32-位
速度: 266MHz
連通性: EBI/EMI,以太網(wǎng),I²C,IrDA,Microwire,SPI,SSI,SSP,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,電機控制 PWM,PWM,WDT
輸入/輸出數(shù): 51
程序存儲器類型: ROMless
RAM 容量: 256K x 8
電壓 - 電源 (Vcc/Vdd): 0.9 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 3x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 296-TFBGA
包裝: 托盤
配用: 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250
568-4742-ND - MODULE DIMM LPC2478 ARM7
622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250
其它名稱: 568-4533
935287084551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
54 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
10.4 Power consumption in Run mode
Power consumption is shown in Figure 5 for WinCE applications running under typical
conditions from SDRAM. MMU and I-cache/D-cache are enabled. The VFP is turned on
but not used. I2S-interface (channel 1), LCD, SLC NAND controller, I2C1-bus, SD card,
touchscreen ADC, and UART 3 are turned on. All other peripherals are turned off.
The AHB clock HCLK is identical to the core clock for frequencies up to 133 MHz, which is
the maximum allowed HCLK frequency. For higher core frequencies, the HCLK PLL
output must be divided by 2 to obtain an HCLK frequency lower than or equal to 133 MHz
resulting in correspondingly lower power consumption by the AHB peripherals.
Conditions: Tamb =25 C; VDD_CORE = 1.2 V for core frequencies 208 MHz;
VDD_CORE = 1.35 V for core frequencies > 208 MHz; VDD(IO) = 1.8 V.
(1) WinCE running from SDRAM; playing wmv file at 20 frames/s, 32 kHz mono.
(2) WinCE running from SDRAM; playing mp3 file at 128 kbit/s, stereo.
(3) WinCE running from SDRAM; no application running.
Fig 5.
Core current versus core frequency for WinCE applications
core frequency (MHz)
40
280
200
120
002aae762
80
40
120
160
IDD(run)
(mA)
0
(1)
(2)
(3)
HCLK = 133 MHz
HCLK = 72 MHz
VDD_CORE =
1.2 V
VDD_CORE =
1.35 V
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