參數(shù)資料
型號(hào)： LPC3250FET296,551
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 17/57頁(yè)
文件大小： 0K
描述： IC ARM9 MCU 256K 296-TFBGA
特色產(chǎn)品： LPC32x0 ARM926EJ-S Processor
標(biāo)準(zhǔn)包裝： 126
系列： LPC3200
核心處理器： ARM9
芯體尺寸： 16/32-位
速度： 266MHz
連通性： EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，電機(jī)控制 PWM，PWM，WDT
輸入/輸出數(shù)： 51
程序存儲(chǔ)器類型： ROMless
RAM 容量： 256K x 8
電壓 - 電源 (Vcc/Vdd)： 0.9 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 296-TFBGA
包裝： 托盤
配用： 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250
568-4742-ND - MODULE DIMM LPC2478 ARM7
622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250
其它名稱： 568-4533
935287084551
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
24 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.
Functional description
7.1 CPU and subsystems
7.1.1 CPU
NXP created the LPC3220/30/40/50 using an ARM926EJ-S CPU core that includes a
Harvard architecture and a 5-stage pipeline. To this ARM core, NXP implemented a 32 kB
instruction cache, a 32 kB data cache and a Vector Floating Point coprocessor. The
ARM926EJ-S core also has an integral Memory Management Unit (MMU) to provide the
virtual memory capabilities required to support the multi-programming demands of
modern operating systems. The basic ARM926EJ-S core V5TE instruction set includes
DSP instruction extensions for native Jazelle Java Byte-code execution in hardware. The
LPC3220/30/40/50 operates at CPU frequencies up to 266 MHz.
7.1.2 Vector Floating Point (VFP) coprocessor
The LPC3220/30/40/50 includes a VFP co-processor providing full support for
single-precision and double-precision add, subtract, multiply, divide, and
multiply-accumulate operations at CPU clock speeds. It is compliant with the IEEE 754
standard for binary Floating-Point Arithmetic. This hardware floating point capability
makes the microcontroller suitable for advanced motor control and DSP applications. The
VFP has 3 separate pipelines for floating-point MAC operations, divide or square root
operations, and Load/Store operations. These pipelines operate in parallel and can
complete execution out of order. All single-precision instructions execute in one cycle,
except the divide and square root instructions. All double-precision multiply and
multiply-accumulate instructions take two cycles. The VFP also provides format
conversions between floating-point and integer word formats.
7.1.3 Emulation and debugging
The LPC3220/30/40/50 supports emulation and debugging via a dedicated JTAG serial
port. An Embedded Trace Buffer allows tracing program execution. The dedicated JTAG
port allows debugging of all chip features without impact to any pins that may be used in
the application.
7.1.3.1
Embedded ICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
Embedded ICE protocol converter. The Embedded ICE protocol converter converts the
Remote Debug Protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel (DCC) function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or entering the
debug state.
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