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參數(shù)資料
| 型號(hào)： | LPC3250FET296,551 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 21/57頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM9 MCU 256K 296-TFBGA |
| 特色產(chǎn)品： | LPC32x0 ARM926EJ-S Processor |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 系列： | LPC3200 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 266MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，I²S，LCD，電機(jī)控制 PWM，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 256K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 0.9 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 296-TFBGA |
| 包裝： | 托盤(pán) |
| 配用： | 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250 568-4742-ND - MODULE DIMM LPC2478 ARM7 622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250 |
| 其它名稱： | 568-4533 935287084551 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
28 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.4 Internal memory
7.4.1 On-chip ROM
The built-in 16 kB ROM contains a program which runs a boot procedure to load code
from one of four external sources, UART 5, SSP0 (SPI mode), EMC Static CS0 memory,
or NAND FLASH.
After reset, execution always begins from the internal ROM. The bootstrap software first
reads the SERVICE input (GPI_1). If SERVICE is LOW, the bootstrap starts a service boot
and can download a program over serial link UART 5 to IRAM and transfer execution to
the downloaded code.
If the SERVICE pin is HIGH, the bootstrap routine jumps to normal boot. The normal boot
process first tests SPI memory for boot information if present it uploads the boot code and
transfers execution to the uploaded software. If the SPI is not present or no software is
loaded, the bootloader will test the EMC Static CS0 memory for the presence of boot code
and if present boots from static memory, If this test fails the boot loader will test external
NAND flash for boot code and boot if code is present.
The boot loader consumes no user memory space because it is in ROM.
7.4.2 On-chip SRAM
On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed
as 8, 16, or 32 bit memory. The LPC3220/30/40/50 provides 256 kB of internal SRAM.
7.5 External memory interfaces
The LPC3220/30/40/50 includes three external memory interfaces, NAND Flash
controllers, Secure Digital Memory Controller, and an external memory controller for
SDRAM, DDR SDRAM, and Static Memory devices.
7.5.1 NAND flash controllers
The LPC3220/30/40/50 includes two NAND flash controllers, one for multi-level cell
NAND flash devices and one for single-level cell NAND flash devices. The two NAND
flash controllers use the same pins to interface to external NAND flash devices, so only
one interface is active at a time.
7.5.1.1
Multi-Level Cell (MLC) NAND flash controller
The MLC NAND flash controller interfaces to either multi-level or single-level NAND flash
devices. An external NAND flash device is used to allow the bootloader to automatically
load a portion of the application code into internal SRAM for execution following reset.
The MLC NAND flash controller supports small (528 byte) and large (2114 byte) pages.
Programmable NAND timing parameters allow support for a variety of NAND flash
devices. A built-in Reed-Solomon encoder/decoder provides error detection and
correction capability. A 528 byte data buffer reduces the need for CPU supervision during
loading. The MLC NAND flash controller also provides DMA support.
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