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| 型號： | LPC3250FET296,551 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 22/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM9 MCU 256K 296-TFBGA |
| 特色產(chǎn)品： | LPC32x0 ARM926EJ-S Processor |
| 標準包裝： | 126 |
| 系列： | LPC3200 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 266MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，I²S，LCD，電機控制 PWM，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 256K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 0.9 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 296-TFBGA |
| 包裝： | 托盤 |
| 配用： | 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250 568-4742-ND - MODULE DIMM LPC2478 ARM7 622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250 |
| 其它名稱： | 568-4533 935287084551 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
29 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.5.1.2
Single-Level Cell (SLC) NAND flash controller
The SLC NAND flash controller interfaces to single-level NAND flash devices. DMA page
transfers are supported, including a 20-byte DMA read and write FIFO. Hardware support
for ECC (Error Checking and Correction) is included for the main data area. Software can
correct a single bit error.
7.5.2 SD card controller
The SD interface allows access to external SD memory cards. The SD card interface
conforms to the SD Memory Card Specification Version 1.01.
7.5.2.1
Features
1-bit and 4-bit data line interface support.
DMA is supported through the system DMA controller.
Provides all functions specific to the SD memory card. These include the clock
generation unit, power management control, command and data transfer.
7.5.3 External memory controller
The LPC3220/30/40/50 includes a memory controller that supports data bus SDRAM,
DDR SDRAM, and static memory devices. The memory controller provides an interface
between the system bus and external (off-chip) memory devices.
The controller supports 16-bit and 32-bit wide SDR SDRAM devices of 64 Mbit, 128 Mbit,
128 Mbit, 256 Mbit, and 512 Mbit sizes, as well as 16-bit wide data bus DDR SDRAM
devices of 64 Mbit, 128 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit sizes. Two dynamic
memory chip selects are supplied, supporting two groups of SDRAM:
DYCS0 in the address range 0x8000 0000 to 0x9FFF FFFF
DYCS1 in the address range 0xA000 0000 to 0xBFFF FFFF
The memory controller also supports 8-bit, 16-bit, and 32-bit wide asynchronous static
memory devices, including RAM, ROM, and flash, with or without asynchronous page
mode. Four static memory chip selects are supplied for SRAM devices:
CS0 in the address range 0xE000 0000 to 0xE0FF FFFF
CS1 in the address range 0xE100 0000 to 0xE1FF FFFF
CS2 in the address range 0xE200 0000 to 0xE2FF FFFF
CS3 in the address range 0xE300 0000 to 0xE3FF FFFF
The SDRAM controller uses three data ports to allow simultaneous requests from multiple
on-chip AHB bus masters and has the following features.
Dynamic memory interface supports SDRAM, DDR-SDRAM, and low-power variants.
Read and write buffers to reduce latency and improve performance.
Static memory features include
– asynchronous page mode read
– programmable wait states
– bus turnaround cycles
– output enable and write enable delays
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