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參數(shù)資料
| 型號(hào)： | LPC3250FET296,551 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 29/57頁 |
| 文件大小： | 0K |
| 描述： | IC ARM9 MCU 256K 296-TFBGA |
| 特色產(chǎn)品： | LPC32x0 ARM926EJ-S Processor |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 系列： | LPC3200 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 266MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART，USB OTG |
| 外圍設(shè)備： | DMA，I²S，LCD，電機(jī)控制 PWM，PWM，WDT |
| 輸入/輸出數(shù)： | 51 |
| 程序存儲(chǔ)器類型： | ROMless |
| RAM 容量： | 256K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 0.9 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 296-TFBGA |
| 包裝： | 托盤 |
| 配用： | 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250 568-4742-ND - MODULE DIMM LPC2478 ARM7 622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250 |
| 其它名稱： | 568-4533 935287084551 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
35 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
7.7.4 Clocking and power control features
7.7.4.1
Clocking
Clocking in the LPC3220/30/40/50 is designed to be versatile, so that system and
peripheral requirements may be met, while allowing optimization of power consumption.
Clocks to most functions may be turned off if not needed and some peripherals do this
automatically.
The LPC3220/30/40/50 supports three operational modes, two of which are specifically
designed to reduce power consumption. The modes are: Run mode, Direct run mode, and
Stop mode.These three operational modes give control over processing speed and power
consumption. In addition, clock rates to different functional blocks may be changed by
switching clock sources, changing PLL values, or altering clock divider configurations.
This allows a trade-off of power versus processing speed based on application
requirements.
7.7.4.2
Crystal oscillator
The main oscillator is the basis for the clocks most chip functions use by default.
Optionally, many functions can be clocked instead by the output of a PLL (with a fixed
397x rate multiplication) which runs from the RTC oscillator. In this mode, the main
oscillator may be turned off unless the USB interface is enabled. If a SYSCLK frequency
other than 13 MHz is required in the application, or if the USB block is not used, the main
oscillator may be used with a frequency of between 1 MHz and 20 MHz.
7.7.4.3
PLLs
The LPC3220/30/40/50 includes three PLLs: The 397x PLL allows boosting the RTC
frequency to 13.008896 MHz for use as the primary system clock. The USB PLL provides
the 48 MHz clock required by the USB block, and the HCLK PLL provides the basis for the
CPU clock, the AHB bus clock, and the main peripheral clock.
The 397x PLL multiplies the 32768 Hz RTC clock by 397 to obtain a 13.008896 MHz
clock. The 397x PLL is designed for low power operation and low jitter. This PLL requires
an external RC loop filter for proper operation.
The HCLK PLL accepts an input clock from either the main oscillator or the output of the
397x PLL. The USB PLL only accepts an input clock from the main oscillator.The USB
input clock runs through a divide-by-N pre-divider before entering the USB PLL.
The input to the HCLK and USB PLLs may initially be divided down by a pre-divider value
‘N’, which may have the values 1, 2, 3, or 4. This pre-divider can allow a greater number of
possibilities for the output frequency. Following the PLL input divider is the PLL multiplier.
This can multiply the pre-divider output by a value ‘M’, in the range of 1 through 256. The
resulting frequency must be in the range of 156 MHz to 320 MHz. The multiplier works by
dividing the output of a Current Controlled Oscillator (CCO) by the value of M, then using
a phase detector to compare the divided CCO output to the pre-divider output. The error
value is used to adjust the CCO frequency.
At the PLL output, there is a post-divider that can be used to bring the CCO frequency
down to the desired PLL output frequency. The post-divider value can divide the CCO
output by 1, 2, 4, 8, or 16. The post-divider can also be bypassed, allowing the PLL CCO
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