MOTOROLA
MC68341 USER'S MANUAL
6- 39
6.9.2 DMA Channel Example Configuration Code
The following are examples of configuration sequences for a DMA channel in single- and
dual-addressing modes.
This common set of equates is used by all of the following examples:
***************************************************************************
* SIM41 equates
***************************************************************************
MBAR
EQU
$0003FF00
Address of SIM41 Module Base Address Reg.
MODBASE
EQU
$FFFFF000
SIM41 MBAR address value
PPARC
EQU
$29
Port C pin assignment register
***************************************************************************
* DMA Channel 1 equates
DMACH1
EQU
$780
Offset from MBAR for channel 1 regs
DMAMCR1
EQU
$0
MCR for channel 1
* Channel 1 register offsets from channel 1 base address
DMAINT1
EQU
$4
interrupt register channel 1
DMACCR1 EQU
$8
control register channel 1
DMACSR1 EQU
$A
status register channel 1
DMAFCR1 EQU
$B
function code register channel 1
DMASAR1 EQU
$C
source address register channel 1
DMADAR1 EQU
$10
destination address register channel 1
DMABTC1 EQU
$14
byte transfer count register channel 1
***************************************************************************
In addition to the initialization shown in each example, the Port C Pin Assignment Register
should also be configured if DTC, RDYx, or delayed DACKx signals are used:
***************************************************************************
* PPARC initialization for DMA signal functionality
* The following example selects RDY1 and delayed DACKx functionality for
* DMA channel 1 - other pins unchanged:
OR.B
#$50,MODBASE+PPARC
Select RDY1 & delayed DACK1 funct
***************************************************************************
Example 1: External Burst Request Generation, Single-Address Transfers.
***************************************************************************
* MC68341 basic DMA channel register initialization example code.
* This code is used to initialize the 68341's internal DMA channel
* registers, providing basic functions for operation.
* The code sets up channel 1 for external burst request generation,
* single-address mode, long word size transfers.
* Control signals are asserted on the DMA read cycle.
***************************************************************************
* Equates
***************************************************************************
SARADD
EQU
$10000
source address
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Freescale Semiconductor, Inc.
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