MOTOROLA
MC68341 USER’S MANUAL
4- 27
The software watchdog timeout period, listed in Table 4-8, gives the formula to derive the
software watchdog timeout for any clock frequency. The timeout periods are listed for a
32.768-kHz crystal used with the VCO and for a 16.777-MHz external oscillator with divide
by one selected by the V-bit of the SYNCR.
Table 4-8. Deriving Software Watchdog Timeout
SWP
SWT1
SWT0
Software Timeout Period
32.768-kHz
Crystal Period
16.777-MHz External
Clock Period
00
0
29/EXTAL Input Frequency
15.6 ms
30
s
00
1
211 /EXTAL Input Frequency
62.5 ms
122
s
01
0
213 /EXTAL Input Frequency
250 ms
488
s
01
1
215 /EXTAL Input Frequency
1 s
1.95 ms
10
0
218 /EXTAL Input Frequency
8 s
15.6 ms
10
1
220 /EXTAL Input Frequency
32 s
62.5 ms
11
0
222 /EXTAL Input Frequency
128 s
250 ms
11
1
224 /EXTAL Input Frequency
512 s
1 s
NOTE:
When the SWP and SWT bit s are modified to select a software timeout other than the default, the
software service sequence ($55 followed by $AA written to the software service register ) must be
performed before the new timeout period takes effect. Refer to 4.2.2.5 Software Watchdog for
more information.
DBFE—Double Bus Fault Monitor Enable
1 = Enable double bus fault monitor function.
0 = Disable double bus fault monitor function.
For more information, see 4.2.2.3 Double Bus Fault Monitor and Section 5 CPU32.
BME—Bus Monitor External Enable
1 = Enable bus monitor function for an internal-to-external bus cycle.
0 = Disable bus monitor function for an internal-to-external bus cycle.
For more information see 4.2.2.2 Internal Bus Monitor.
BMT1, BMT0—Bus Monitor Timing
These bits select the timeout period for the bus monitor (see Table 4-9). Upon reset, the
bus monitor is set to 512 system clocks.
Table 4-9. BMTx Encoding
BMT1
BMT0
Bus Monitor Timeout Period
0
512 system clocks (CLKOUT)
0
1
256 system clocks
1
0
128 system clocks
1
64 system clocks
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Freescale Semiconductor, Inc.
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