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MC68341 USER’S MANUAL
MOTOROLA
The duty cycle of the waveform generated on TOUT can be dynamically changed by
writing new values into PREL1 and/or PREL2. If PREL1 or PREL2 is being accessed
simultaneously by the counter logic and a CPU32 write, the old preload value may actually
get loaded into the counter at time-out. If at time-out, the counting logic was accessing
PREL2 and the CPU32 was writing to PREL1 (or vice versa), there would be no
unexpected results.
8.3.4 Variable-Width Single-Shot Pulse Generator
This mode is used to produce a one-time pulse that has a delay controlled by the value
stored in PREL1 and a duration controlled by the value stored in PREL2. With TOUT
programmed to change state, this sequence creates a single pulse of variable width. This
mode can be selected by programming the CR MODE bits to 011.
The timer is enabled by setting both the SWR and CPE bits in the CR and, if TGATE is
enabled (TGE bit in the CR is set), then asserting TGATE. When the timer is enabled, the
ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded
with the value stored in the PREL1 register (N1). With each successive falling edge of the
counter clock, the counter decrements. The time between enabling the timer and the first
time-out can range from N1 to N1 + 1 periods. When TGATE is used to enable the
counter, the enabling of the timer is asynchronous; however, if timing is carefully
considered, the time to the first time-out can be known. For additional details on timing,
see Section 12 Electrical Characteristics.
If the counter counts down to the value stored in the COM, the COM and TC bits in the SR
are set. The counter continues counting down to time-out. At this time, the SR TO bit is set
and the SR COM bit is cleared. The next falling edge of the counter clock after time-out
causes the value in PREL2 (N2) to be loaded into the counter, and the counter begins
counting down from this value. After the second time-out, the selected clock is held high,
disabling the prescaler and counter. Additionally, the SR ON and COM bits are cleared.
TOUT behaves as a variable-width pulse when the OCx bits of the CR are programmed
for toggle mode. TOUT is a logic zero between the time that the timer is enabled and the
first time-out. When this event occurs, TOUT transitions to a logic one. The second time-
out occurs after N2 + 1 periods (allowing for the zero cycle), resulting in TOUT returning to
a logic zero (see Figure 8-7). The OUT bit in the SR reflects the level of TOUT.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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