參數(shù)資料
型號(hào)： MSX340PB480
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： DSP-CROSSBAR SWITCH, PBGA480
封裝： 37.50 X 37.50 MM, 1.27 MM PITCH, MO-149, TBGA-480
文件頁數(shù)： 13/33頁
文件大?。?/td> 651K
代理商： MSX340PB480
Preliminary
www.fairchildsemi.com
20
M
SX340
AC Electrical Characteristics (T
A = 0°C to 70°C, VDD = 3.3V ±10%)
Refer to Figure 7 for AC test conditions.
Symbol
Parameter
Min
Max
Units
RDATA
NRZ Data Rate
150
Mb/s
fRIO
Registered Input/Output Clock Frequency
75
MHz
tW_RIO
Registered Clock Pulse Width, High or Low
3
ns
tS_RI
Registered Input Setup Time to Clock
5
ns
tS_RO
Registered Output Setup Time to Clock
9.5
ns
tH_RI
Registered Input Clock to Hold Data
0
ns
tH_RO
Registered Output Clock to Hold Data
0
ns
tCO_RO
Registered Output Clock to Data Out Valid
11
ns
tCO_RI
Registered Input Clock to Data Out Valid
24
ns
tPHL, tPLH
One Way Signal Propagation Delay, Fanout = 1
20
ns
tMC Delta
Additional Delay Per Output Multicast (MC) Mode
2
ns
tW+
Input Flow-through Positive Pulse Width
6
tW-
Input Flow-through Negative Pulse Width
6
tSK
Skew
4ns
tPZH_IT,
Input Enable to Valid Data
20
ns
tPZL_IT
tPZH_OT,
Output Enable to Valid Data
7.5
ns
tPZL_OT
tPZH_OT,
Output Enable to High Z State
7.5
ns
tPZL_OT
tRC
RapidConfigure Clock Period
20
ns
tW+_RC
RapidConfigure Clock Pulse Width
8
ns
tW-_RC
tS_RC
RapidConfigure Address Setup to RC Clock
1
ns
tH_RC
RapidConfigure Address Hold Time to RC Clock
4
ns
tP_RC
Read Back Access Time
9ns
tP_RD
RC_RDY to Readback Data Valid
4
ns
tP_UD
Update of Crosspoint to Data Out
10
ns
fJTAG
JTAG Clock Frequency (TCK)
8MHz
tW_JTAG
JTAG Clock Pulse Width (TCK) at 8 MHz Cycle
48
72
ns
tS_JTAG
JTAG Setup Time
4
ns
tH_JTAG
JTAG Hold Time
0
ns
tP_JTAG
JTAG Clock to Output Data Valid (TDO)
10
ns
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