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參數(shù)資料
| 型號： | MSX340PB480 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | DSP-CROSSBAR SWITCH, PBGA480 |
| 封裝： | 37.50 X 37.50 MM, 1.27 MM PITCH, MO-149, TBGA-480 |
| 文件頁數(shù)： | 30/33頁 |
| 文件大?。?/td> | 651K |
| 代理商： | MSX340PB480 |
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Preliminary
www.fairchildsemi.com
6
M
SX340
Introduction (Continued)
TABLE 1. Summary for Programmable I/O Attributes for MSX Devices
Symbol
I/O Port Function
Mnemonic
Input
The external signal is buffered from the Input Port pin to the
corresponding Switch Matrix line.
IN
Output
The internal signal is buffered from the corresponding
Switch Matrix line to the Output Port pin. In this mode an
optional output enable (OE) can be selected. The default
level is logic 0. The output data inversion mode is available
to invert the output signal.
OP
Registered
Input
The external signal at the I/O Port is registered into an edge-
triggered register within the I/O Port. A clock source is
required in this mode. An input enable (IE) is available but
not required.
RI
Registered
Output
The internal signal on the Switch Matrix line is registered by
an edge-triggered register within the I/O Port. A clock source
is required in this mode. An output enable (OE) is available
but not required.
RO
The output data inversion mode is NOT available to invert
the output signal.
Bidirectional
Transceiver
In this mode, the I/O buffer acts as a bidirectional transceiver
between the I/O Port pin and the corresponding Switch
Matrix line. This mode requires an input enable (IE) and out-
put enable (OE).
BT
The output data inversion mode is available to invert the out-
put signal.
Bus
Repeater
In the Bus Repeater mode, the I/O Port behaves as a wire
(with a non-zero propagation delay). This unique feature
patented by Fairchild incorporates as self-sensing circuit to
determine signal direction and does not require a direction
control signal.
BR
When multiple I/O Ports, configured as “Bus Repeater”, are
connected together through the Switch Matrix to form a sin-
gle internal node, any (open collector or 3-STATABLE) LOW
(logic “0”) external signal appearing at any one of the I/O
Ports gets repeated (or broadcast) to other I/O Ports. For
more details, refer to the Technical Note: “The Bus Repeater
Mode”
Pin Side
Force 0
In this output mode, the I/O Port pin is forced LOW (logic 0),
regardless of the signal on the corresponding switch Matrix
line. In this mode an optional output enable (OE) can be
selected.
F0
Pin Side
Force 1
In this output mode, the I/O Port pin is forced HIGH (logic 1),
regardless of the signal on the corresponding Switch Matrix
line. In this mode an optional output enable (OE) can be
selected.
F1
No Connect
In this mode, the I/O Port pin is isolated from the Switch
Matrix. This is done by 3-STATING both the input and output
part of the I/O buffer.
NC
Array Side
Force 0
In this input mode, the Switch Matrix line is forced LOW
(logic 0), regardless of the signal on the corresponding I/O
Port. In this mode an optional input enable (IE) can be
selected.
A0
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