Preliminary
3
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MSX340
Introduction (Continued)
Input and Output Buffers (I/O Buffers)
Each signal in the switch matrix is connected to a program-
mable I/O buffer, which is independently configured
through either the RapidConfigure or JTAG Interface. The
I/O buffer attributes include its signal direction (input, out-
put or bi-directional) and data flow mode (flow-through or
registered). The signal can also be inverted at the output.
Trickle current source (normally 15
A) on the pin side and
array side for each I/O Port and control pin is used to pull
unused or non-driven circuits to a stable high level. Figure
3 shows a basic block diagram of an I/O buffer with the
sources for the three control signals (IE, OE and CLK). For
any given port number, these three control signals can be
selected from one of two sources. The control signals are
explained in more detail in the following section.
FIGURE 3. MSX I/O Buffer Block Diagram
I/O Port Function Mode
The following legend describes the various modes of the
Input or Output Ports and the specification used by the
Fairchild Development System Software for bitstream gen-
eration.
Legend:
Ax
= Switch Matrix Signal
Px
= I/O Port Signal
IE
= Input Enable
OE
= Output Enable (Active LOW)
CLK
= Clock
Next-Neighbor Clocking
Included among the clocking options in MSX340 is the abil-
ity to use an adjacent port as a clock source. This is
referred to as a Next-Neighbor Clock. In the MSX340,
Port 0 can be clocked by Port 1, which can be clocked by
Port 2, which can be clocked by Port 3, etc. Since each I/O
buffer can be programmed as an input or an output (among
other options) there are four ways to utilize the next neigh-
bor clock option.
Note: The MSX340 is a bondout option of the MSX532 and as such not
every port can utilize the next neighbor clocking option. Please refer to port
cross reference guide table in the “MSX Family Register Programming
Manual”. The following ports do not have the next neighbor clock option:
P009, P060, P103, P155, P197, P248, P288, P339.
Switch
Matrix
OUT
IN
BR
I/O
Port
CLK_IN
CLK_OUT
IE
OE
{
V
DD
V
SS
{
Next
Neighbor
CLK
Sources
CLK
Sources
Next
Neighbor
{