參數(shù)資料
型號(hào): MSX340PB480
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 數(shù)字信號(hào)處理外設(shè)
英文描述: DSP-CROSSBAR SWITCH, PBGA480
封裝: 37.50 X 37.50 MM, 1.27 MM PITCH, MO-149, TBGA-480
文件頁(yè)數(shù): 31/33頁(yè)
文件大?。?/td> 651K
代理商: MSX340PB480
Preliminary
7
www.fairchildsemi.com
MSX340
Introduction (Continued)
Array Side
Force 1
In this input mode, the Switch Matrix line is forced HIGH
(logic 1), regardless of the signal on the corresponding I/O
Port. In this mode an optional input enable (IE) can be
selected.
A1
Bidirectional
Transceiver
with
Register
Input
This mode combines Registered Input and buffered Output
(OP). This mode requires a clock source (CLK), and input
enable (IE) and output enable (OE).
BT & RI
Bidirectional
Transceiver
with
Register
Output
This mode combines Registered Output (RO) and buffered
Input (IE). This mode requires a clock source (CLK), and
input enable (IE) and output enable (OE).
BT & RO
The output data inversion mode is NOT available to invert
the output signal.
Bidirectional
Transceiver
with
Register I/O
This mode combines Registered Input (RI) and Registered
Output (RO). This mode requires a clock source (CLK), and
input enable (IE) and output enable (OE).
BT, RI &
RO
The output data inversion mode is NOT available to invert
the output signal.
DQ
IE
Ax
Px
CLK
OE
DQ
IE
Ax
Px
CLK
OE
D
1
Q
1
IE
Ax
Px
CLK_IN
OE
CLK_OP
Q
0
D
0
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