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參數(shù)資料
| 型號： | MSX340PB480 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | DSP-CROSSBAR SWITCH, PBGA480 |
| 封裝： | 37.50 X 37.50 MM, 1.27 MM PITCH, MO-149, TBGA-480 |
| 文件頁數(shù)： | 27/33頁 |
| 文件大?。?/td> | 651K |
| 代理商： | MSX340PB480 |
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Preliminary
33
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MSX340
340
Port
Di
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Glossary (Continued)
Device ID: A 32-bit register in the MSX device with a wired
identification. The ID consists of a given number for the
device and a revision history field. The identification is
shifted out during JTAG reset and the DEVICE ID instruc-
tion in JTAG mode. The ID for the MSX devices is
0x0000A89F.
Extest: A JTAG instruction that samples I/O pin states and
loads new I/O buffer states for testing device pin connec-
tions. The MSX devices use a special test mode in Extext
to observe the buffer data on the pin side and the array
side. A bit in the Control Register controls this mode.
I/O Buffer: The circuit that controls the driving of its associ-
ated pin and its port into and out of the Crosspoint Array.
The buffer contains all the circuits to make it independent
of the other I/O Buffers. Each Buffer contains registers for
input and output, driving circuits for input and output, sense
for Crosspoint Array input, and RAM bits to hold pro-
grammed data controlling the function of the buffer.
Input or Output Path: The signal flow from pin to array
and array to pin. Each path has a register with selectable
clocks, drivers for the loaded outputs with selectable
enables, and sense circuits to detect changes on either
side of the I/O Buffer.
JTAG: The Joint Test Action group is a committee to stan-
dardize scan testing of devices. The JTAG interface is
referred to as IEEE 1149.1. This is a five bit serial program-
ming and testing method.
JTAG Sequence: The ordering of all the pins in a serial
chain for driving and sensing signals on pins during Extest
and Sample/Preload. All pins except power and ground
and the five JTAG pins are in the serial string.
Next Neighbor: Input can be selected as the clock for the
I/O buffer registers for data and clock pairing. The next
higher port is the selected neighbor except for Port 531,
which uses Port 0.
Pin Side Driver: The I/O Buffer circuit that drives the
device pin associated with that buffer.
Port: A name followed by a number to identify a pin on the
device. Ports are numbered from 531 to 0 on the MSX
device. In shifting sequence, Port P000 is shifted in first
and shifted out first.
RapidConfigure: A parallel programming method for the
MSX devices. The RC mode uses 29 dedicated pins to pro-
gram the Crosspoint Array and the I/O Buffers. The 29 pins
consist of an enable, a strobe, two instruction bits, four
variable bits, and two ten-bit address fields.
RCE: A control pin of the MSX device that is sampled dur-
ing reset to determine if the device becomes active in the
JTAG or the RapidConfigure mode. This pin places the
Control Register bit in the state to allow RC operations or
not based on the voltage level of the RCE pin. The JTAG
mode is always enabled and can set or clear the RC bit in
the Control Register.
Trickle Current: A very low current (~15 microamperes)
used to pull unused or non-driven circuits to a stable high
level. Prevents signals from drifting between CMOS thresh-
olds and drawing currents from the power supply. In the
case of Bus Repeater, the small trickle current provides a
known high level on the pin and array side inputs.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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