參數(shù)資料
型號(hào)： MSX340PB480
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： DSP-CROSSBAR SWITCH, PBGA480
封裝： 37.50 X 37.50 MM, 1.27 MM PITCH, MO-149, TBGA-480
文件頁(yè)數(shù)： 9/33頁(yè)
文件大小： 651K
代理商： MSX340PB480
Preliminary
17
www.fairchildsemi.com
MSX340
Introduction (Continued)
Device Reset Options
At power-on, all MSX340 I/O buffers are set as flow-
through inputs (IN) with input enable ON, and the switch
matrix set to all no connects (NC).
The RapidConfigure reset, hardware reset, and JTAG reset
functions will program the I/O buffers to flow-through input
(IN) mode with input enable ON, and each Loading SRAM
cell in the Switch Matrix is set to No Connect. An UPDATE
signal is required to complete the operation and set the
Active SRAM cells to No Connect.
The JTAG interface can be reset via the TRST pin or by
clocking five consecutive one to the TMS pin. The hard-
ware reset pin can be done accomplished through the
HW_RST pin (Active LOW). RC reset can be accomplished
by applying the RC instruction 1101 to the RCI[3:0] pins.
Device Reset Options
Note 3: TLR
= Test Logic Reset state.
Note 4: NC
= No Connect. Each Loading SRAM cell in the Switch Matrix is updated to No Connect. An UPDATE signal is required to complete the operation
and set the Active SRAM cells to No Connect.
Programming
Reset
I/O
Switch
RCE Mode
JTAG
Interface
Method
Ports
Matrix
Control
TAP
Hardware Reset
Power-On Reset
IN
NC
1 (RC Enabled) TLR (Note 3)
HW_RST (Low Pulse)
IN
NC (Note 4) 1 (RC Enabled)
TLR
JTAG Reset
1. Low Pulse on TRST
Unchanged Unchanged
Unchanged
TLR
2. TMS High for 5 SCLK Cycles
Unchanged Unchanged
Unchanged
TLR
3. Device Reset (Instruction 1101)
IN
NC (Note 4) 1 (RC Enabled)
TLR
4. Reset Crosspoint Array (Instruction 1101
Unchanged NC (Note 4)
Unchanged
RapidConfigure Reset 1. Device Reset (Instruction 1101)
IN
NC (Note 4) 1 (RC Enabled)
Unchanged
2. Reset Crosspoint Array (Instruction 0010) Unchanged NC(Note 4)
Unchanged
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