
Preliminary
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2
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SX340
FIGURE 1. MSX340 Functional Block Diagram
Introduction
Switch Matrix
The MSX family are SRAM-based, bit-oriented switching
devices. The main functional block of the device is a Switch
Matrix as shown in Figure 1. The Switch Matrix is an x-y
routing structure (or grid). Each horizontal signal trace is
hardwired to a corresponding vertical signal trace as
shown by the junction dots. An I/O Port pin connects to this
horizontal-vertical trace pair through a programmable
buffer. Signal paths through the Switch Matrix are well bal-
anced, resulting in predictable and uniform pin-to-pin
delays.
The two SRAM cells (shown in Figure 2) are arranged so
that a double buffered scheme can be employed. The
Active SRAM cells are responsible for establishing connec-
tions in the switch matrix by turning ON a pass transistor,
while the Loading SRAM cell can be used to store a sec-
ond configuration that can be transferred to the Active
SRAM cell at any time. If the UPDATE signal is asserted
high, the contents of the Loading SRAM cell are transferred
to the Active SRAM cell and the switch matrix connection is
either made or broken.
The UPDATE signal can be used to control when the
switch matrix is reconfigured. For instance, as long as the
UPDATE signal is de-asserted (held LOW), the Loading
SRAM cells for the entire switch matrix could be changed
without affecting the current configuration of the switch.
When the UPDATE signal is asserted high, the entire
switch matrix would be reconfigured simultaneously. If the
UPDATE signal is asserted continuously, all crosspoint pro-
gramming commands (generated by JTAG or RapidConfig-
ure programming cycles) will take effect immediately, since
the Loading SRAM cell’s contents will be transferred
directly to the Active SRAM cell.
FIGURE 2. MSX Switch Matrix Diagram