參數(shù)資料
型號(hào)： MSX340PB480
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： DSP-CROSSBAR SWITCH, PBGA480
封裝： 37.50 X 37.50 MM, 1.27 MM PITCH, MO-149, TBGA-480
文件頁數(shù)： 8/33頁
文件大?。?/td> 651K
代理商： MSX340PB480
Preliminary
www.fairchildsemi.com
16
M
SX340
Introduction (Continued)
TABLE 9. JTAG Input Format
TABLE 10. JTAG Instructions
Instruction
Control
Address
Bit Number
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
13
12
11
10
C1
C0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
15 14 13 12
Instruction
Description
1
1 Bypass
Places device in a mode to pass TDI data to TDO with one clock delay. Used
for programming and testing devices through serial connected JTAG con-
trols.
1
0 Control Bit
Sets and clears the control bit A0 (LSB)
1
0
1 IO Buffer and
Crosspoint Array Reset,
Device ID out
Resets I/O buffers for the Ports to Input and clear all Ports to Disconnect.
The device ID is serialized out to TDO. The Instruction serialized out is the
RESET Instruction during the Instruction phase. Update is forced to the cros-
spoint array
1
0
0 Device ID out
Serialize the device ID and revision history out to TDO. ID for the MSX340 is
0x0000A89F.
1
0
1
1 Set the JTAG Address
Register
Set the 10-bit JTAG Address Register with the lower ten bits of the JTAG
Instruction Register. The lower ten bits of the JTAG Address Register
become the ’B’ Address for Crosspoint Access.
1
0
1
0 Access the Crosspoint Array
and Update Array
Read or Write the crosspoint addressed by the lower ten bits of the JTAG
Instruction (A Address) and the JTAG Address Register or Address Counter
(B Address). Read data is shifted out on TDO.
C1 C0 = 0 0 Read Switch with A and B Address.
Increment ’B’ address with each ShiftDR.
C1 C0 = 0 1 Connect switch at location Addressed with A and B.
Increment ’B’ address with each ShiftDR. Activate with UpdateDR.
C1 C0 = 1 0 Disconnect switch at location Addressed with A and B.
Increment ’B’ address with each ShiftDR. Activate with UpdateDR.
C1 C0 = 1 1 Force update of Switch Array Shadow register.
Activate with UpdateDR.
1
0
1 Disconnect a Port in the
Crosspoint Array
Disconnect all Ports from the Port Addressed by the lower ten bits of the
JTAG Instruction. The addressed port is reset to disconnect. The pro-
grammed state of the I/O buffer is not changed.
1
0
0 Clear the Crosspoint Array
Clear the crosspoint array at no-connect. Leave the I/O buffers unchanged.
0
1
1 Shift the IO Buffer Data
Register
Shift twenty bits of data into and out of the I/O Buffer Data Register. The data
is used to program the I/O buffers. Parallel shift twenty bits into I/O buffer
Copy Register.
0
1
0 Shift out the I/O Buffer Copy
Register
Shifts twenty bits of data out of the I/O Buffer Copy Register. Data is either
the I/O buffer Data register shifted in by instruction 0111 or the last JTAG I/O
buffer Read Data.
0
1
0
1 Access an I/O Buffer
Read or write the I/O buffer addressed with the lower ten bits of the JTAG
Instruction. Read data is placed in the twenty-bit I/O buffer Copy Register.
Write Data for the I/O buffer is from the I/O buffer Data Register.
C1 C0 = 0 0 Read an I/O buffer date into the Copy Register.
C1 C0 = 0 1 Write an I/O buffer with data in I/O buffer Data Register.
0
1
0
Not used.
0
1
1 Test mode only
for programming device with
RapidConfigure through JTAG
Fairchild only - internal test mode to test RapidConfigure through JTAG.
0
1
0 Crosspoint Array Write Testing,
Write one location per ShiftDR
Instruction Address = Lower Limit = A, Address Register = Upper Limit = B.
C1 = 1, C0 = 1 Connect all ports in address range
C1 = 1, C0 = 0 Connect Pattern = A[1] XOR B[1]
C1 = 0, C0 = 0 Connect Pattern = A[4]
C1 = 0, C0 = 1 Connect Pattern = NOT (A[1] XOR B[1]). Compliment
address limits, Address is complimented to test A-High Port to B-Low Port
connections. Other three patterns test opposite. The number of cycles =
(Sum of (X = 1), where X = Low Limit to X = High Limit) - 1
0
0 Sample/Preload EXTEST
External scan tests for interconnect testing.
0
1 Sample/Preload EXTEST
External scan tests for interconnect testing.
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