參數(shù)資料
型號： MSX340PB480
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 數(shù)字信號處理外設(shè)
英文描述： DSP-CROSSBAR SWITCH, PBGA480
封裝： 37.50 X 37.50 MM, 1.27 MM PITCH, MO-149, TBGA-480
文件頁數(shù)： 10/33頁
文件大小： 651K
代理商： MSX340PB480
Preliminary
www.fairchildsemi.com
18
M
SX340
Pin Description
Pin Name
Type
Description
P[339:000] Bi-directional Input/Output Signals.
OE[3:0]
Input
Global Output Enables. Each output enable can control two of the four I/O banks.
Signal
MSX340 Connected I/O’s
OE_0
P255-P339, P000-P084
OE_1
P000-P084, P085-P169
OE_2
P085-P169, P170-P254
OE_3
P170-P254, P255-P339
IE[3:0]
Input
Global Input Enables. Each input enable can control two of the four I/O banks.
Signal
MSX340 Connected I/O’s
IE_0
P255-P339, P000-P084
IE_1
P000-P084, P085-P169
IE_2
P085-P169, P170-P254
IE_3
P170-P254, P255-P339
UPDATE
Input
Global Update
CLK[3:0]
Input
Global Clocks. Each clock can control two of the four I/O banks.
Signal
MSX340 Connected I/O’s
CLK_0
P255-P339, P000-P084
CLK_1
P000-P084, P085-P169
CLK_2
P085-P169, P170-P254
CLK_3
P170-P254, P255-P339
HW_RST
Input
Hardware Reset.
RCE
Input
RapidConfigure Mode Select
Programing mode is determined at power up or HW_RST
0 = JTAG mode (RapidConfigure disabled)
1 = RapidConfigure mode (JTAG, I/O buffer, Crosspoint programming disabled)
Note: Device can be reconfigured from JTAG to RC or from RC to JTAG in the JTAG mode without HW_RST or power
up. In RapidConfigure mode the programming of the I/O buffers and crosspoint array through JTAG is disabled, but the
JTAG port can still be used for boundary scan testing.
RC Pins
RC_CLK
Input
RapidConfigure Clock.
RC_EN
Input
RapidConfigure Cycle Enable.
RCA[9:0]
Bi-directional RapidConfigure Address A.
RCB[9:0]
Bi-directional RapidConfigure Address B.
RCC[0]
Bi-directional RapidConfigure Program Variable C.
RCC[3:1]
Input
RapidConfigure Program Variable C.
RCI[1:0]
Input
RapidConfigure Instruction Bits.
RC_RDY
Output
Read out I/O buffer and connect/disconnect status.
JTAG Pins
TCK
Input
JTAG Test Clock.
TDI
Input
JTAG Test Data In.
TDI
Output
JTAG Test Data Out.
TMS
Input
JTAG Test Mode Select.
TRST
Input
JTAG Test and JTAG Scan Reset.
Power and Ground Pins
VDD
Power
+3.3V power for the chip.
VSS
Ground
Ground for the chip. Tie these pins to system ground.
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