參數(shù)資料
型號(hào)： MSX340PB480
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： DSP-CROSSBAR SWITCH, PBGA480
封裝： 37.50 X 37.50 MM, 1.27 MM PITCH, MO-149, TBGA-480
文件頁(yè)數(shù)： 6/33頁(yè)
文件大?。?/td> 651K
代理商： MSX340PB480
Preliminary
www.fairchildsemi.com
14
M
SX340
Introduction (Continued)
TABLE 7. I/O Buffer Programming Commands (Continued)
JTAG Interface
The dedicated JTAG TAP interface is designed in compli-
ance with the IEEE-1149.1. The standard interface has five
pins: Test Data Out (TDO), Test Mode Select (TMS), Test
Data In (TDI), Test Reset (TRST), and Test Clock (TCK)
which allow Boundary Scan Testing as well as device con-
figuration and verification. Data on the TDI and TMS pins
are clocked into the device on the rising edge of the TCK
signal, while the valid data appears on the TDO pin after
the falling edge of TCK. For more detailed information on
JTAG programming, refer to the MSX Family Register Pro-
gramming Manual.
I/O Buffer Programming
The JTAG I/O buffer Data Register where data is held, is
used to program the I/O buffer. This register is used with
the JTAG interface only. The JTAG I/O buffer Data Register
is 20 bits wide. Power on reset, RapidConfigure reset,
Hardware reset, and JTAG reset programs all Ports as
inputs. JTAG can be reset via the TRST pin or by clocking
five consecutive ones to the TMS pin. The HW_RST (hard-
ware reset) pin resets and breaks all connections in the
Crosspoint Array to all no-connects, and the I/O buffers to
inputs.
Table 8 lists the bits and their function in JTAG mode.
These are internal bits as shifted into the I/O buffer Data
register for I/O buffer Programming.
TABLE 8. I/O Buffer Programming Bit Functions
Note 1: If both IE1 and IE2 are selected, the two are assigned an OR function to form the IE. Either can be “1” to enable the input.
Note 2: If both OE1 and OE2 are selected, active low signals are assigned an AND function to form the resulting OE. Either can be “0” to enable the output.
Signal
Description
RCB[1]
Inverted Input Clock. When this bit is set to a one, the registered input port’s selected clock source will be
inverted. When zero the input clock source will not be inverted.
RCB[0]
Inverted Output Clock. When this bit is set to a one, the registered output port’s selected clock source will be
inverted. When zero the output clock source will not be inverted.
Bit Number
I/O Buffer Function
Description
0
Input (IN)
Input Pin Data to Drive Array
1
Output (OP)
Output Array Data to Pin
2
Bus Repeater (BR)
Low Array Signal, Drive Pin LOW
Low Pin Signal, Drive Array LOW
3
Reg In Clock 1
Selects Reg. In I/O Buffer, Clock 1
4
Reg In Clock 2
Selects Reg. In I/O Buffer, Clock 2
5
Reg In Clock Neighbor
Selects Reg. In I/O Buffer, Neighbor
6
Reg Out Clock 1
Selects Reg. Out I/O Buffer, Clock 1
7
Reg Out Clock 1
Selects Reg. Out I/O Buffer, Clock 2
8
Reg Out Clock Neighbor Selects Reg. Out I/O Buffer, Neighbor
9
Input Enable 1 (IE1)
Select Input Enable 1 (Note 1)
10
Input Enable 2 (IE2)
Select Input Enable 2 (Note 1)
11
Output Enable 1 (OE1)
Select Output Enable 1 (Note 2)
12
Output Enable 2 (OE2)
Select Output Enable 2 (Note 2)
13
Force 1
Force I/O Buffer Output Pin to a 1
14
Force 0
Force I/O Buffer Output Pin to a 0
15
Array 1
Force I/O Buffer Array to a 1
16
Array 0
Force I/O Buffer Array to a 0
17
Invert Output
Output data is inverted.
This operation is invalid in Bus Repeater mode and Register Output mode
18
Invert Input Clock
Invert the clock to the input register
19
Invert Output Clock
Invert the clock to the output register
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