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| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 15/78頁 |
| 文件大?。?/td> | 610K |
| 代理商： | PENTIUM III |
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Datasheet
15
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
2.2.7
Clock Control
BCLK provides the clock signal for the processor and on die L2 cache. During AutoHALT Power
Down and Stop-Grant states, the processor will process a system bus snoop. The processor does
not stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance
into the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
When the processor is in Sleep and Deep Sleep states, it does not respond to interrupts or snoop
transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the
Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache is
restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor
has re-entered Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
2.3
Power and Ground Pins
The operating voltage of the Pentium
III
processor for the PGA370 socket is the same for the core
and the L2 cache; V
CCCORE
. There are four pins defined on the package for voltage identification
(VID). These pins specify the voltage required by the processor core. These have been added to
cleanly support voltage specification variations on current and future processors.
For clean on-chip power and voltage reference distribution, the Pentium
III
processors in the
FC-PGA package have 75 V
CCCORE
, 8 V
REF
, 15 V
TT
, and 77 V
SS
(ground) inputs. V
CCCORE
inputs supply the processor core, including the on-die L2 cache. V
TT
inputs (1.5V) are used to
provide an AGTL+ termination voltage to the processor, and the V
REF
inputs are used as the
AGTL+ reference voltage for the processor. Note that not all V
TT
inputs must be connected to the
V
TT
supply. Refer to
Section 5.3
for more details.
On the motherboard, all V
CCCORE
pins must be connected to a voltage island (an island is a portion
of a power plane that has been divided, or an entire plane). In addition, the motherboard must
implement the V
TT
pins as a voltage island or large trace. Similarly, all GND pins must be
connected to a system ground plane.
Three additional power related pins exist on a processors utilizing the PGA370 socket. They are
V
CC1.5
, V
CC2.5
and V
CCCMOS
.
The V
CCCMOS
pin provides the CMOS voltage for the pull-up resistors required on the system
platform. A 2.5V source must be provided to the V
CC2.5
pin and a 1.5V source must be provided
to the V
CC1.5
pin. The source for V
CC1.5
must be the same as the one supplying V
TT
. The processor
routes the compatible CMOS voltage source (1.5V or 2.5V) through the package and out to the
V
CCCMOS
output pin. Processors based on 0.25 micron technology (e.g., the Intel Celeron
processor) utilize 2.5V CMOS buffers. Processors based on 0.18 micron technology (e.g., the
Pentium
III
processor for the PGA370 socket) utilize 1.5V CMOS buffers. The signal V
COREDET
can be used by hardware on the motherboard to detect which CMOS voltage the processor requires.
A V
COREDET
connected to V
SS
within the processor indicates a 1.5V requirement on V
CCCMOS
.
Refer to
Figure 5
.
Each power signal must meet the specifications stated in
Table 6 on page 24
.
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