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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 30/78頁 |
| 文件大?。?/td> | 610K |
| 代理商： | PENTIUM III |
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30
Datasheet
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25V at the processor pin.
All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.
4. Valid delay timings for these signals are specified into 50
to 1.5V, V
REF
at 1.0 V ±2% and with 56
on-die
R
.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
systems, RESET# should be synchrounous.
7. Specification is for a minimum 0.40 V swing from V
REF
- 200 mV to V
REF
+ 200 mV. This assumes an edge
rate of 0.3V/ns.
8. Specification is for a maximum 1.0 V swing from V
TT
- 1V to V
TT
. This assumes an edge rate of 3V/ns.
9. This should be measured after V
CC
, V
TT
, Vcc
, and BCLK become stable.
10.This specification applies to the Pentium III processor running at 100 MHz system bus frequency.
11.This specification applies to the Pentium III processor running at 133 MHz system bus frequency.
12.BREQ signals at 133 MHz system bus observe a 1.2 ns minimum setup time.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after V
CC
CORE
, V
TT
, V
CCCMOS
, and BCLK become stable.
Table 12. System Bus AC Specifications (AGTL+ Signal Group)
1, 2, 3
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL+ Output Valid Delay
0.40
3.25
ns
8
4, 10, 11
T8: AGTL+ Input Setup Time
1.20
0.95
ns
ns
9
9
5, 6, 7, 10
5, 6, 7, 11, 12
T9: AGTL+ Input Hold Time
1.00
ns
9
8, 10
T10: RESET# Pulse Width
1.00
ms
10
6, 9, 10
Table 13. System Bus AC Specifications (CMOS Signal Group)
1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
Notes
T14: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
8
Active and
Inactive states
T15: PWRGOOD Inactive Pulse Width
10
BCLKs
8
,
11
5
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