參數(shù)資料
型號： pentium III
廠商： Intel Corp.
英文描述： pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器)
中文描述： 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座）
文件頁數(shù)： 71/78頁
文件大?。?/td> 610K
代理商： PENTIUM III
Datasheet
71
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
CPUPRES#
O
The CPUPRES# signal is defined to allow a system design to detect the presence of
a terminator device or processor in a PGA370 socket. Combined with the VID
combination of VID[3:0]= 1111 (see
Section 2.6
), a system can determine if a socket
is occupied, and whether a processor core is present. See the table below for states
and values for determining the presence of a device.
D[63:0]#
I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data
path between the processor system bus agents, and must connect the appropriate
pins on all such agents. The data driver asserts DRDY# to indicate a valid data
transfer.
DBSY#
I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the processor system bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the appropriate
pins on all processor system bus agents.
DEFER#
I
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all processor system bus agents.
DEP[7:0]#
I/O
The DEP[7:0]# (Data Bus ECC Protection) signals provide optional ECC protection
for the data bus. They are driven by the agent responsible for driving D[63:0]#, and
must connect the appropriate pins of all processor system bus agents which use
them. The DEP[7:0]# signals are enabled or disabled for ECC protection during
power on configuration.
DRDY#
I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-cycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all processor system bus agents.
EDGCTRL
O
The EDGCTRL input adjusts the edge rate of AGTL+ output buffers for previous
processors and should be pulled up to V
CC
with a 51
±
5% resistor. See the
platform design guide for implementation details. This signal is not used by the
Pentium III processor.
FERR#
O
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting.
Table 33. Signal Description (Sheet 4 of 8)
Name
Type
Description
PGA370 Socket Occupation Truth Table
Signal
Value
Status
CPUPRES#
VID[3:0]
0
Anything other
than ‘1111’
Processor core installed in the PGA370
socket.
CPUPRES#
VID[3:0]
0
1111
Terminator device installed in the
PGA370 socket (i.e., no core present).
CPUPRES#
VID[3:0]
1
Any value
PGA370 socket not occupied.
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