參數(shù)資料
型號(hào)： pentium III
廠商： Intel Corp.
英文描述： pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動(dòng)帶PGA370插孔奔III處理器)
中文描述： 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動(dòng)帶PGA370插孔奔三處理器的PGA370插座）
文件頁(yè)數(shù)： 75/78頁(yè)
文件大?。?/td> 610K
代理商： PENTIUM III
Datasheet
75
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
7.2
Signal Summaries
Table 34
through
Table 37
list attributes of the processor output, input, and I/O signals.
TRDY#
I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready
to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all processor system bus agents.
TRST#
I
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. TRST# must
be driven low during power on Reset.
VID[3:0]
O
The VID[3:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to V
SS
on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on processors. See
Table 2
for definitions of these
pins. The power supply must supply the voltage that is requested by these pins, or
disable itself.
V
COREDET
O
The V
COREDET
pin indicate the type of processor core present. This pin will float for
2.0V V
CC
CORE
based processor and will be shorted to V
SS
for the Pentium III
processor.
V
CC1.5
I
The V
CC1.5
V input pin provides the termination voltage for CMOS signals interfacing
to the processor. The Pentium III processor reroutes the 1.5V input to the
V
CCCMOS
output via the package. The supply for V
CC1.5
V must be the same one used to
supply V
TT.
V
CC2.5
I
The V
CC2.5
V input pin provides the termination voltage for CMOS signals interfacing
to processors which require 2.5V termination on the CMOS signals. This signal is
not used by the Pentium III processor.
V
CCCMOS
O
The
V
CCCMOS
pin provides the CMOS voltage for use by the platform and is used for
terminating CMOS signals that interface to the processor.
V
REF
I
The V
REF
input pins supply the AGTL+ reference voltage, which is typically 2/3 of
V
TT
. V
is used by the AGTL+ receivers to determine if a signal is a logical 0 or a
logical 1.
Table 33. Signal Description (Sheet 8 of 8)
Name
Type
Description
Table 34. Output Signals
Name
Active Level
Clock
Signal Group
CPUPRES#
Low
Asynch
Power/Other
EDGCTRL
N/A
Asynch
Power/Other
FERR#
Low
Asynch
CMOS Output
IERR#
Low
Asynch
CMOS Output
PRDY#
Low
BCLK
AGTL+ Output
TDO
High
TCK
TAP Output
THERMTRIP#
Low
Asynch
CMOS Output
V
COREDET
N/A
Asynch
Power/Other
VID[3:0]
N/A
Asynch
Power/Other
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