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| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 27/78頁 |
| 文件大小： | 610K |
| 代理商： | PENTIUM III |
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Datasheet
27
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
2.12
AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to V
TT
. These termination resistors are placed electrically between the ends of the signal
traces and the V
TT
voltage supply and generally are chosen to approximate the system platform
impedance. The valid high and low levels are determined by the input buffers using a reference
voltage called V
REF
. Refer to the appropriate platform design guide for more information
Table 9
below lists the nominal specification for the AGTL+ termination voltage (V
TT
). The
AGTL+ reference voltage (V
REF
) is generated on the system motherboard and should be set to 2/3
V
TT
for the processor and other AGTL+ logic. It is important that the baseboard impedance be
specified and held to a ±15% tolerance, and that the intrinsic trace capacitance for the AGTL+
signal group traces is known and well-controlled. For more details on the AGTL+ buffer
specification, see the
Intel
Pentium
II Processor Developer's Manual
and AP-585,
Intel
Pentium
II Processor AGTL+ Guidelines
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III
processors at all frequencies.
2. Pentium III processors for the PGA370 socket contain AGTL+ termination resistors on the processor die,
except for the RESET# input.
3. V
TT
and Vcc
must be held to 1.5V ±9%. It is required that V
TT
and Vcc
be held to 1.5V ±3% while the
processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom
side of the baseboard.
4. The value of the on-die R
is determined by the resistor value measured by the RTTCTRL signal pin. See
Section 7.0
for more details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific
chipset/processor combination.
5. V
REF
is generated on the motherboard and should be 2/3 V
TT
±2% nominally. Insure that there is adequate
V
REF
decoupling on the motherboard.
2.13
System Bus AC Specifications
The processor system bus timings specified in this section are defined at the socket pins on the
bottom of the motherboard. Unless otherwise specified, timings are tested at the processor pins
during manufacturing. Timings at the processor pins are specified by design characterization. See
Section 7.0
for the processor signal definitions.
Table 10
through
Table 16
list the AC specifications associated with the processor system bus.
These specifications are broken into the following categories:
Table 10
contains the system bus
clock specifications,
Table 12
contains the AGTL+ specifications,
Table 13
contains the CMOS
signal group specifications,
Table 14
contains timings for the reset conditions,
Table 15
and covers
APIC bus timing, and
Table 16
covers TAP timing.
All processor system bus AC specifications for the AGTL+ signal group are relative to the rising
edge of the BCLK input. All AGTL+ timings are referenced to V
REF
for both ‘0’ and ‘1’ logic
levels unless otherwise specified.
Table 9. Processor AGTL+ Bus Specifications
1, 2
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
TT
On-die R
TT
V
REF
Bus Termination Voltage
Termination Resistor
Bus Reference Voltage
1.50
V
V
3
4
5
40
130
1.05
0.950
2/3 V
TT
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