參數(shù)資料
型號: pentium III
廠商: Intel Corp.
英文描述: pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器)
中文描述: 奔騰III處理器在500MHz到933MHz的(工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座)
文件頁數(shù): 36/78頁
文件大?。?/td> 610K
代理商: PENTIUM III
36
Datasheet
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
3.0
Signal Quality Specifications
Signals driven on the processor system bus should meet signal quality specifications to ensure that
the components read data properly and to ensure that incoming signals do not affect the long term
reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in
Table 17
,
Table 18
, and
Table 23
ensures that
signal quality effects will not adversely affect processor operation.
3.1
BCLK and PICCLK Signal Quality Specifications and
Measurement Guidelines
Table 17
describes the signal quality specifications at the processor pins for the processor system
bus clock (BCLK) and APIC clock (PICCLK) signals.
Figure 14
describes the signal quality
waveform for the system bus clock at the processor pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits.
This specification is an absolute value.
Table 17. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins
1
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: BCLK V
IL
0.500
V
14
V1: PICCLK V
IL
0.700
V
14
V2: BCLK V
IH
2.000
V
14
V2 PICCLK V
IH
2.000
V
14
V3: V
IN
Absolute Voltage Range
–0.58
3.18
V
14
V4: BCLK Rising Edge Ringback
2.000
V
14
2
V4: PICCLK Rising Edge Ringback
2.000
V
14
2
V5: BCLK Falling Edge Ringback
0.500
V
14
2
V5: PICCLK Falling Edge Ringback
0.700
V
14
2
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