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參數(shù)資料
| 型號： | pentium III |
| 廠商： | Intel Corp. |
| 英文描述： | pentium III Processor for the PGA370 Socket at 500MHz to 933MHz(工作頻率500到933兆赫茲活動帶PGA370插孔奔III處理器) |
| 中文描述： | 奔騰III處理器在500MHz到933MHz的（工作頻率500到933兆赫茲活動帶PGA370插孔奔三處理器的PGA370插座） |
| 文件頁數(shù)： | 17/78頁 |
| 文件大小： | 610K |
| 代理商： | PENTIUM III |
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Datasheet
17
Pentium
III Processor for the PGA370 Socket at 500 MHz to 933 MHz
2.5
Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the system bus interface. All AGTL+
system bus timing parameters are specified with respect to the rising edge of the BCLK input. See
the
P6 Family of Processors Hardware Developer's Manual
for further details.
2.5.1
Mixing Processors of Differrent Frequencies
In two-way MP (multi-processor) systems, mixing processors of different internal clock
frequencies is not supported and has not been validated. Pentium
III
processors do not support a
variable multiplier ratio; therefore, adjusting the ratio setting to a common clock frequency is not
valid. However, mixing processors of the same frequency but of different steppings is supported.
Details on support for mixed steppings is provided in the
Pentium
III
Processor Specification
Update
.
Note:
Not all Pentium
III
processors for the PGA370 socket are validated for use in dual processor (DP)
systems. Refer to the
Pentium
III
Processor Specification Update
to determine which processors
are DP capable.
2.6
Voltage Identification
There are four voltage identification pins on the PGA370 socket. These pins can be used to support
automatic selection of V
CCCORE
voltages. These pins are not signals, but are either an open circuit
or a short circuit to V
SS
on the processor. The combination of opens and shorts defines the voltage
required by the processor core. The VID pins are needed to cleanly support voltage specification
variations on current and future processors. VID[3:0] are defined in
Table 2
. A ‘1’ in this table
refers to an open pin and a ‘0’ refers to a short to ground. The voltage regulator or VRM must
supply the voltage that is requested or disable itself.
To ensure a system is ready for current and future processors, the range of values in
bold
in
Table
2
should be supported. A smaller range will risk the ability of the system to migrate to a higher
performance processor and/or maintain compatibility with current processors.
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