參數(shù)資料
型號(hào)： SZF2002HL
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80
文件頁(yè)數(shù)： 10/76頁(yè)
文件大小： 431K
代理商： SZF2002HL
1998 Aug 26
10
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
8
FUNCTIONAL DESCRIPTION
Detailed descriptions of each function are described in:
Chapter 9 “Memory organization”
Chapter 10 “Program Status Word (PSW)”
Chapter 11 “I/O facilities”
Chapter 12 “Timer/event counters”
Chapter 13 “Pulse Width Modulated output”
Chapter 14 “Analog-to-digital converter (ADC)”
Chapter 15 “Reduced power modes”
Chapter 16 “I2C-bus serial I/O”
Chapter 17 “Standard serial interface SIO0: UART”
Chapter 18 “Interrupt system”
Chapter 19 “Clock circuitry”
Chapter 20 “Reset”
Chapter 21 “Special Function Registers overview”
Chapter 22 “Debugging support”.
8.1
General
The SZF2002 is a stand-alone high-performance CMOS
microcontroller designed for use in real-time applications
such as wireless telephone and mobile communications,
instrumentation, industrial control, intelligent computer
peripherals and consumer products.
The device provides hardware features, architectural
enhancements and new instructions to function as a
controller for applications requiring up to 256 kbytes of
program memory and/or up to 6144 + 256 bytes of on-chip
data memory.
The SZF2002 contains a 6-kbyte program memory; a
static 6144 + 256 byte data memory (RAM); 24 I/O lines;
three 16-bit timer/event counters; a fifteen-source two
priority-level, nested interrupt structure, a 6-channel 8-bit
ADC, a Watchdog Timer and a Pulse Width Modulation
output.
Two serial interfaces are provided on-chip:
A standard UART serial interface
A standard I
2
C-bus serial interface with a transfer speed
of up to 400 kbits/s (depending on clock frequency).
The I
2
C-bus serial interface has byte oriented master
and slave functions allowing communication with the
whole family of I
2
C-bus compatible devices.
The device has two software selectable modes of reduced
activity for power reduction:
Idle mode:
freezes the CPU while allowing the
derivative functions (timers, serial I/O, RAM,
ADC and PWM) and interrupt system to continue
functioning
Power-down mode:
saves the RAM contents but stops
the clock causing all other chip functions to be
inoperative.
8.2
CPU timing
A machine cycle consists of a sequence of 6 states. Each
state lasts one clock period, thus a machine cycle takes
6 clock periods or 1
μ
s if the clock frequency (f
clk
) is
6 MHz.
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