參數(shù)資料
型號(hào): SZF2002HL
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
中文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80
文件頁(yè)數(shù): 66/76頁(yè)
文件大?。?/td> 431K
代理商: SZF2002HL
1998 Aug 26
66
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
27 AC CHARACTERISTICS
Table 56
Timing with respect to CE, OE and WE
SYMBOL
PARAMETER
MIN.
TYP
MAX.
UNIT
General
(see Fig.29)
t
XCLKH
t
XCLKL
T
cy(XCLK)
XCLK HIGH time
XCLK LOW time
XCLK cycle time
31.25
31.25
62.5
ns
ns
ns
Memory Access
(Figs 29 and 30)
t
(CEL-OEL)1
t
(OEL)1
t
(CEH-OEH)1
t
(CEL)1
t
(CEL-WEL)1
t
(WEL)1
t
(CEH-WEH)1
t
su(OE-D)2
t
su(CEL-D)2
t
su(D-WEL)3
t
(CEL-DV)3
t
su(D-SM)2
t
h(SM-D)2
t
h(WEH-D)3
t
h(CEH-D)3
t
su(A-CEL)1
t
h(CEH-A)1
t
(CEL-OEL)4
t
(OEL)4
t
(CEH-OEH)4
CE LOW to OE LOW (data cycle)
OE LOW time (data cycle)
CE HIGH to OE HIGH (data cycle)
CE LOW time (data cycle)
CE LOW to WE LOW (data cycle)
WE LOW time (data cycle)
CE HIGH to WE HIGH (data cycle)
Data set-up time from OE (data read cycle)
Data set-up time from CE LOW (data read cycle)
Data set-up time to WE LOW (data write cycle)
Data valid time from CE LOW (data write cycle)
Data set-up time to sample moment (data read cycle); note 1
Data hold time from sample moment (data read cycle); note 1
Data hold time from WE HIGH (data write cycle)
Data hold time from CE HIGH (data write cycle)
Address set-up time to CE LOW (data cycle)
Address hold time from CE HIGH (data cycle)
CE LOW to OE LOW (code fetch cycle)
OE LOW time (code fetch cycle)
CE HIGH to OE HIGH (code fetch cycle)
0
0
0
0
1
2
t
CLK
+ 3
7
2
t
CLK
+ 7
12
4t
CLK
1
2
t
CLK
+ 5
7
2
t
CLK
+ 8
13
3t
CLK
18
7
2
t
CLK
18
1
2
t
CLK
3
3
8
t
CLK
20
t
CLK
10
1
2
t
CLK
5
t
CLK
1
2
t
CLK
3
2
t
CLK
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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