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參數(shù)資料
| 型號： | SZF2002HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 8-bit microcontroller with 6-kbyte embedded RAM |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 28/76頁 |
| 文件大小： | 431K |
| 代理商： | SZF2002HL |
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1998 Aug 26
28
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
15.4
Status of external pins
The status of the external pins during Idle and Power-down mode is shown in Table 20.
Table 20
Status of external pins during Idle and Power-down modes
15.5
Power Control Register (PCON)
Idle and Power-down modes are activated by software using this SFR. PCON is not bit addressed, the reset value of
PCON is 00000000B.
Table 21
Power Control Register (SFR address 87H)
Table 22
Description of PCON bits
MODE
MEMORY
CE
OE
PWM
PORTS 1, 3
AND 4
DATA BUS
Idle
internal
external
internal
external
1
1
1
1
1
1
1
1
active
active
port data
port data
port data
port data
Port 0 data
floating
Port 0 data
floating
Power-down
halted in last state
halted in last state
7
6
5
4
3
2
1
0
SMOD
ARD
RFI
WLE
GF1
GF0
PD
IDL
BIT
SYMBOL
DESCRIPTION
7
SMOD
Double Baud rate.
When set to a logic 1 the baud rate is doubled when the serial port
SIO0 is being used in modes 1, 2 or 3 (except when Timer 2 is used).
Setting this bit will force all MOVX instructions to access off-chip memory instead of
AUX RAM.
RFI reduction mode.
Setting this bit will disable the ALE toggling during on-chip
memory access. The SZF2002 does not have this signal during operational mode, but
setting this bit will reduce the number of chip selects (CE) of the external memory (and
thus power).
Watchdog Load Enable.
This flag must be set by software prior to loading the
Watchdog Timer (T3). It is cleared when T3 is loaded.
General purpose flag 1.
General purpose flag 0.
Power-down mode selection.
Setting this bit activates the Power-down mode. If a
logic 1 is written to both PD and IDL at the same time, PD takes precedence.
Idle mode selection.
Setting this bit activates the Idle mode.
6
ARD
5
RFI
4
WLE
3
2
1
GF1
GF0
PD
0
IDL
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