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參數資料
| 型號： | SZF2002HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 8-bit microcontroller with 6-kbyte embedded RAM |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80 |
| 文件頁數： | 17/76頁 |
| 文件大?。?/td> | 431K |
| 代理商： | SZF2002HL |
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1998 Aug 26
17
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
11 I/O FACILITIES
11.1
Ports
The SZF2002 has 24 I/O lines: ports P1, P3 and P4 of
which ports P1 and P3 are bit addressed (P0 and P2 are
always used as address/data bus). Ports 0 to 4 have the
following alternative functions:
Port 0 Used internally.
Port 1 Used for a number of special functions:
Provides the inputs for the external interrupts:
INT2 to INT8
The I
2
C-bus interface: SCL and SDA
Counter inputs: T2 and T2EX.
Port 2 Used internally.
Port 3 Pins can be configured individually to provide:
External interrupt request inputs: INT1 and INT0
Counter input: T1 and T0
UART input and output: RXD and TXD.
Port 4 Provides chip select for external data memory:
RAMCE.
To enable a port pin alternative function, the port bit latch
in its SFR must contain a logic 1.
Each port consists of a latch (SFRs P0 to P4), an output
driver and input buffer. Ports 1, 3 and 4 have internal
pull-ups (except P1.6 and P1.7). Figure 8 shows that the
strong transistor ‘p1’ is turned on for only 2 clock periods
after a LOW-to-HIGH transition in the port latch. When on,
it turns on ‘p3’ (a weak pull-up) through the inverter. This
inverter and ‘p3’ form a latch which holds the logic 1.
In Port 0 the pull-up ‘p1’ is only on when emitting logic 1s
for external memory access.
11.2
Port configuration
The port pins (except for P1.6 and P1.7) are configured as
shown in Fig.8. This is a quasi-bidirectional I/O with
pull-up. The strong booster pull-up ‘p1’ is turned on for one
clock period after a LOW-to-HIGH transition in the port
latch. All port pins will be set to HIGH during reset.
Fig.8 Port configuration.
handbook, full pagewidth
MBK456
p1
p2
p3
input data
read port pin
2 clock
periods
n
strong pull-up
I/O pin
VDD
Q
from port latch
INPUT
BUFFER
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