參數(shù)資料
型號： SZF2002HL
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80
文件頁數(shù)： 69/76頁
文件大?。?/td> 431K
代理商： SZF2002HL
1998 Aug 26
69
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
Table 57
Timing figures with respect to RAMCE, OE and WEL
Notes
1.
Sample moment for data read cycles is on negative clock edge in state S3, the internal clock skew must be taken
into account also. This results in 3t
CLK
10 ns from OE LOW (or
7
2
t
CLK
10 ns from RAMCE LOW) maximum.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
General
(see Fig.29)
t
XCLKH
t
XCLKL
T
cy(XCLK)
XCLK HIGH time
XCLK LOW time
XCLK cycle time
31.25
31.25
62.5
ns
ns
ns
Memory Access
(Figs 29 and 30)
t
(RCEL-OEL)
t
(OEL)
t
(RCEH-OEH)
t
(RCEL)
t
(RCEL-WEL)
t
(WEL)
t
(RCEH-WEH)
t
su(OEL-D)
t
su(RCEL-D)
t
su(D-WEL)
t
(RCEL-DV)
t
su(D-SM)
t
h(SM-D)
t
h(WEH-D)
t
h(RCEH-D)
t
su(A-RCEL)
t
h(RCEH-A)
t
su(DZ-OEL)
t
h(OEH-DZ)
RAMCE LOW to OE LOW
OE LOW time
RAMCE HIGH to OE HIGH
RAMCE LOW time
RAMCE LOW to WE LOW
WE LOW time
RAMCE HIGH to WE HIGH
Data set-up time from OE LOW
Data set-up time from RAMCE LOW
Data set-up time to WE LOW
Data valid time from RAMCE LOW
Data set-up time to sample moment, note 1
Data hold time from sample moment; note 1
Data hold time from WE HIGH
Data hold time from RAMCE HIGH
Address set-up time to RAMCE LOW
Address hold time from RAMCE HIGH
Data bus high-impedance set-up time to OE LOW
Data bus high-impedance hold time from OE HIGH
0
0
0
1
2
t
CLK
+ 1
1
2
t
CLK
10
1
2
t
CLK
3
7
2
t
CLK
+ 8
6
4t
CLK
1
1
2
t
CLK
2
7
2
t
CLK
+ 7
7
3t
CLK
18
7
2
t
CLK
20
1
2
t
CLK
+ 3
4
8
t
CLK
7
t
CLK
14
1
2
t
CLK
t
CLK
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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