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參數(shù)資料
| 型號： | SZF2002HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 8-bit microcontroller with 6-kbyte embedded RAM |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 64/76頁 |
| 文件大?。?/td> | 431K |
| 代理商： | SZF2002HL |
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1998 Aug 26
64
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
2.
The operating supply current is measured with all output pins disconnected; CLK driven with t
r
= t
f
= 10 ns;
V
IL
= V
SS
; V
IH
= V
DD
; EA = RST = Port 0 = V
DD
.
The Idle mode supply current is measured with all output pins disconnected; CLK driven with t
r
= t
f
= 10 ns; V
IL
= V
SS
;
V
IH
= V
DD
; EA = Port 0 = V
DD
.
The power-down current is measured with all output pins disconnected; CLK connected to V
SS
; EA = Port 0 = V
DD
;
RST = V
SS
.
The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I
2
C-bus specification. Therefore, an input voltage
below 0.3V
DD
will be recognized as a logic 0 and an input voltage above 0.7V
DD
will be recognized as a logic 1.
3.
4.
5.
26 ADC CHARACTERISTICS
Notes
1.
2.
3.
All ADC inputs require an external divide-by-2 voltage divider.
Gain error: the maximum difference between actual and ideal slope.
Zero-offset error: the difference between the actual and ideal input voltage corresponding to the first actual code
transition.
Differential non-linearity: the difference between the actual and ideal code widths.
Integral non-linearity: maximum deviation from straight line.
Channel-to-channel matching: the difference between corresponding code transitions of actual characteristics taken
from different channels under the same temperature, voltage and frequency conditions. Not tested, but verified on
sampling basis.
4.
5.
6.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
IN(ADC)
V
DDA
I
DDA
C
AIN
R
AIN
G
e
OS
e
DNL
INL
M
ctc
ADC input voltage
analog supply voltage
supply current operating
analog on-chip input capacitance
analog on-chip input impedance
Gain error; note 2
zero-offset error; note 3
differential non-linearity; note 4
Integral non-linearity; note 5
channel-to-channel matching;
note 6
input voltage slope
note 1
V
SSA
V
DD
0.5
10
1
1
0.5
1
0.5V
DDA
V
DD
+ 0.5
0.5
2
+1
+1
+0.5
+1
±
1
2
V
V
mA
pF
M
%
LSB
LSB
LSB
LSB
V
DDA
= 3.0 V; f
clk
= 8 MHz
V
I(slope)
f
clk
= 8 MHz
0.15
+0.15
V/ms
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