參數(shù)資料
型號(hào)： SZF2002HL
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Low voltage 8-bit microcontroller with 6-kbyte embedded RAM
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80
文件頁(yè)數(shù)： 67/76頁(yè)
文件大小： 431K
代理商： SZF2002HL
1998 Aug 26
67
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
Notes
1.
Sample moment for data read cycles is on negative clock edge in state S3, the internal clock skew must be taken
into account also. This results in 3t
CLK
10 ns from OE LOW (or
7
2
t
CLK
10 ns from CE LOW) maximum.
Sample moment for code fetch cycles is on negative clock edge in state S2 or S4, the internal clock skew must be
taken into account also. This results in
3
2
t
CLK
10 ns from OE LOW (or 2t
CLK
10 ns from CE LOW) maximum.
t
(CEL)4
t
su(OE-D)4
t
su(CEL-D)4
t
su(D-SM)4
t
h(SM-D)4
t
su(DZ-OEL)
CE LOW time (code fetch cycle)
Data set-up time from OE (code fetch cycle)
Data set-up time from CE LOW (code fetch cycle)
Data set-up time to sample moment (code fetch cycle), note 2
Data hold time from sample moment (code fetch cycle)
Data bus high-impedance set-up time to OE LOW
(data read cycle); (Code Fetch cycle)
Data bus high-impedance hold time from OE HIGH
(data read cycle); (code fetch cycle)
Address set-up time to CE LOW (code fetch cycle)
Address hold time from CE HIGH (code fetch cycle)
0
1
2
t
CLK
+ 12
2t
CLK
3
2
t
CLK
18
2t
CLK
18
8
ns
ns
ns
ns
ns
ns
t
h(DZ-OEH)
1
2
t
CLK
2;
t
CLK
11
ns
t
su(A-CEL)4
t
h(CEH-A)4
1
2
t
CLK
4
1
2
t
CLK
ns
ns
SYMBOL
PARAMETER
MIN.
TYP
MAX.
UNIT
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