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參數(shù)資料
| 型號(hào)： | SZF2002HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 8-bit microcontroller with 6-kbyte embedded RAM |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80 |
| 文件頁(yè)數(shù)： | 22/76頁(yè) |
| 文件大?。?/td> | 431K |
| 代理商： | SZF2002HL |
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1998 Aug 26
22
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
12.5
Watchdog Timer (T3)
In addition to Timer 2 and the standard timers, a Watchdog
Timer (consisting of an 11-bit prescaler and an 8-bit timer)
is also available.
The Watchdog Timer is controlled by the Watchdog
Enable Register (WDTKEY). When WDTKEY = 55H, the
timer is disabled and the Power-down mode is enabled.
Otherwise, the timer is enabled and the Power-down mode
is disabled. In the Idle mode the Watchdog Timer and reset
circuitry remain active.
The Watchdog Timer is shown in Fig.11.
The timer frequency is derived from the clock frequency
using the formula shown below:
When a timer overflow occurs, the microcontroller is reset.
To prevent a system reset the timer must be reloaded in
time by the application software.
f
timer
f
6
2048
×
(
)
T3
×
------------------------------------------
=
If the processor suffers a hardware/software malfunction,
the software will fail to reload the timer.This failure will
produce a reset upon overflow thus preventing the
processor running out of control.
The Watchdog Timer can only be reloaded if the condition
flag WLE (PCON.4) has been previously set by software.
At the moment the counter is loaded the condition flag is
automatically cleared. After reset the Watchdog Timer is
off. The Watchdog Timer is started by loading a value into
T3.
The time interval between the timer reloading and the
occurrence of a reset is dependent upon the reloaded
value. The time interval is derived from the clock and the
value programmed into T3 and may be calculated as
shown below:
For example, this time period may range from 2 to 500 ms
when using a clock frequency f
clk
= 6 MHz.
T
reload
--256
T3
–
)
f
timer
=
Fig.11 Functional diagram of the Watchdog Timer (T3).
handbook, full pagewidth
MGM141
INTERNAL BUS
write
T3
PRESCALER
11-BIT
CLEAR
TIMER T3 (8-BIT)
LOAD
overflow
internal
reset
LOADEN
SFR WDTKEY
LOADEN
PCON.4
PCON.1
CLEAR
WLE
PD
RRST
RST
INTERNAL BUS
fclk/6
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