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參數(shù)資料
| 型號： | SZF2002HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 8-bit microcontroller with 6-kbyte embedded RAM |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 26/76頁 |
| 文件大?。?/td> | 431K |
| 代理商： | SZF2002HL |
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1998 Aug 26
26
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
14.1
ADC Control Register (ADCON)
Table 15
ADC Control Register (SFR address C4H)
Table 16
Description of ADCON bits
Table 17
Selection of analog input channel
14.2
ADC Result Register (ADCH)
Table 18
ADC Result Register (SFR address C5H)
Table 19
Description of ADCH bits
7
6
5
4
3
2
1
0
CKDIV
ADCI
ADCS
AADR2
AADR1
AADR0
BIT
SYMBOL
CKDIV
DESCRIPTION
7
6
5
These 2 bits are reserved.
Prescaler select.
When CKDIV = 1, the ADC clock prescaler is used (divide-by-2).
Prescaling is necessary with clocks over 8 MHz.
ADC interrupt flag.
This flag is set when an ADC conversion result is ready to be read.
An interrupt is invoked if this is enabled (EAD). This flag must be cleared by software,
(it cannot be set by software).
ADC start and status flag.
When this bit is set an ADC conversion is started. ADCS
must be set by software. The ADC logic ensures that this signal is HIGH while the ADC
is busy. On completion of the conversion ADCI is set and one clock later the ADCS flag
is reset. ADCS cannot be reset by software.
Analog input select.
These bits are used to select one of the six analog inputs;
see Table 17.
4
ADCI
3
ADCS
2
1
0
AADR2
AADR1
AADR0
AADR2
AADR1
AADR0
SELECTED CHANNEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
reserved
reserved
7
6
5
4
3
2
1
0
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
BIT
SYMBOL
DESCRIPTION
7 to 0
ADC7 to ADC0
8-bit ADC result
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