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參數(shù)資料
| 型號： | SZF2002HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low voltage 8-bit microcontroller with 6-kbyte embedded RAM |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 52/76頁 |
| 文件大?。?/td> | 431K |
| 代理商： | SZF2002HL |
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1998 Aug 26
52
Philips Semiconductors
Product specification
Low voltage 8-bit microcontroller with
6-kbyte embedded RAM
SZF2002
19 CLOCK CIRCUITRY
The SZF2002 is clocked with an external digital clock.
The input must be driven with a digital square wave.
Note that the duty cycle influences the timing to the
external components, since both the positive and negative
clock edges are used.
20 RESET
To initialize the SZF2002 a reset is performed by either of
two methods:
Applying an external signal to the RST pin
Watchdog Timer overflow.
20.1
External reset using the RST pin
The reset input for the SZF2002 is RST. A reset is
accomplished by holding the RST pin HIGH for at least two
machine cycles (12 clock periods) while the clock is
running. The CPU responds by executing an internal reset.
Port pins adopt their reset state immediately after the RST
goes HIGH. During reset, WE and OE, and CE are held
HIGH.
The external reset is asynchronous to the internal clock.
The RST pin is sampled during state 5, phase 2 of every
machine cycle. After a HIGH is detected at the RST pin, an
internal reset is repeated until RST goes LOW. The reset
circuitry is also affected by the Watchdog Timer as
described in Section 12.5. The internal RAM is not
affected by reset. When V
DD
is turned on, the RAM
contents are indeterminate.
20.2
Power-on-reset
The device contains on-chip circuitry which switches the
port pins to HIGH as soon as RST goes HIGH. The user
must ensure that the RST pin is held HIGH until the
external clock has stabilised. When RST goes LOW a
further 3 cycles elapse before execution starts.
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