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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 2-2. TCI6482 Memory Map Summary (continued)
MEMORY BLOCK DESCRIPTION
EMAC Descriptor Memory
Reserved
RapidIO Control Registers
Reserved
RapidIO CPPI RAM
Reserved
Reserved
Reserved
Reserved
Reserved
McBSP 0 Data
Reserved
McBSP 1 Data
Reserved
VLYNQ
UTOPIA Receive (Rx) Data Queue
UTOPIA Transmit (Tx) Data Queue
Reserved
Reserved
PCI External Memory Space
TCP2 Data Registers
VCP2 Data Registers
Reserved
EMIFA (EMIF64) Configuration Registers
DDR2 Memory Controller Configuration Registers
Reserved
Reserved
EMIFA CE2 - SBSRAM/Async
(1)
Reserved
EMIFA CE3 - SBSRAM/Async
(1)
Reserved
EMIFA CE4 - SBSRAM/Async
(1)
Reserved
EMIFA CE5 - SBSRAM/Async
(1)
Reserved
DDR2 Memory Controller CE0 - DDR2 SDRAM
Reserved
BLOCK SIZE (BYTES)
8K
496K
256K
768K
16K
2M - 16K
16M
192M
256M
256M
256
64M - 256
256
64M - 256
64M
1K
1K
16M - 2K
48M
256M
128M
128M
256M
128M
128M
256M
256M
8M
256M - 8M
8M
256M - 8M
8M
256M - 8M
8M
256M - 8M
256M
256M
HEX ADDRESS RANGE
02C8 2000 - 02C8 3FFF
02C8 4000 - 02CF FFFF
02D0 0000 - 02D3 FFFF
02D4 0000 - 02DF FFFF
02E0 0000 - 02E0 3FFF
02E0 4000 - 02FF FFFF
0300 0000 - 03FF FFFF
0400 0000 - 0FFF FFFF
1000 0000 - 1FFF FFFF
2000 0000 - 2FFF FFFF
3000 0000 - 3000 00FF
3000 0100 - 33FF FFFF
3400 0000 - 3400 00FF
3400 0100 - 37FF FFFF
3800 0000 - 3BFF FFFF
3C00 0000 - 3C00 03FF
3C00 0400 - 3C00 07FF
3C00 0800 - 3CFF FFFF
3D00 0000 - 3FFF FFFF
4000 0000 - 4FFF FFFF
5000 0000 - 57FF FFFF
5800 0000 - 5FFF FFFF
6000 0000 - 6FFF FFFF
7000 0000 - 77FF FFFF
7800 0000 - 7FFF FFFF
8000 0000 - 8FFF FFFF
9000 0000 - 9FFF FFFF
A000 0000 - A07F FFFF
A080 0000 - AFFF FFFF
B000 0000 - B07F FFFF
B080 0000 - BFFF FFFF
C000 0000 - C07F FFFF
C080 0000 - CFFF FFFF
D000 0000 - D07F FFFF
D080 0000 - DFFF FFFF
E000 0000 - EFFF FFFF
F000 0000 - FFFF FFFF
(1)
The EMIFA CE0 and CE1 are
not
functionally supported on the TCI6482 device, and therefore, are
not
pinned out.
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