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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 5-10. Megamodule L1/L2 Memory Protection Registers (continued)
HEX ADDRESS RANGE
0184 AC04
0184 AC08
0184 AC0C - 0184 ACFF
0184 AD00
0184 AD04
0184 AD08
0184 AD0C
0184 AD10
0184 AD14
0184 AD18 - 0184 ADFF
0184 AE00 - 0184 AE3C
(3)
0184 AE40
0184 AE44
0184 AE48
0184 AE4C
0184 AE50
0184 AE54
0184 AE58
0184 AE5C
0184 AE60
0184 AE64
0184 AE68
0184 AE6C
0184 AE70
0184 AE74
0184 AE78
0184 AE7C
0184 AE80 - 0185 FFFF
ACRONYM
L1DMPFSR
L1DMPFCR
-
L1DMPLK0
L1DMPLK1
L1DMPLK2
L1DMPLK3
L1DMPLKCMD
L1DMPLKSTAT
-
-
L1DMPPA16
L1DMPPA17
L1DMPPA18
L1DMPPA19
L1DMPPA20
L1DMPPA21
L1DMPPA22
L1DMPPA23
L1DMPPA24
L1DMPPA25
L1DMPPA26
L1DMPPA27
L1DMPPA28
L1DMPPA29
L1DMPPA30
L1DMPPA31
-
REGISTER NAME
L1D memory protection fault status register
L1D memory protection fault command register
Reserved
L1D memory protection lock key bits [31:0]
L1D memory protection lock key bits [63:32]
L1D memory protection lock key bits [95:64]
L1D memory protection lock key bits [127:96]
L1D memory protection lock key command register
L1D memory protection lock key status register
Reserved
Reserved
L1D memory protection page attribute register 16
L1D memory protection page attribute register 17
L1D memory protection page attribute register 18
L1D memory protection page attribute register 19
L1D memory protection page attribute register 20
L1D memory protection page attribute register 21
L1D memory protection page attribute register 22
L1D memory protection page attribute register 23
L1D memory protection page attribute register 24
L1D memory protection page attribute register 25
L1D memory protection page attribute register 26
L1D memory protection page attribute register 27
L1D memory protection page attribute register 28
L1D memory protection page attribute register 29
L1D memory protection page attribute register 30
L1D memory protection page attribute register 31
Reserved
(3)
These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C64x+
megamaodule. These registers are not supported for the TCI6482 device.
Table 5-11. CPU Megamodule Bandwidth Management Registers
HEX ADDRESS RANGE
0182 0200
0182 0204
0182 0208
0182 020C
0182 0210 - 0182 02FF
0184 1000
0184 1004
0184 1008
0184 100C
0184 1010 - 0184 103F
0184 1040
0184 1044
0184 1048
0184 104C
ACRONYM
EMCCPUARBE
EMCIDMAARBE
EMCSDMAARBE EMC Slave DMA Arbitration Control Register
EMCMDMAARBE EMC Master DMA Arbitration Control Resgiter
-
Reserved
L2DCPUARBU
L2D CPU Arbitration Control Register
L2DIDMAARBU
L2D IDMA Arbitration Control Register
L2DSDMAARBU
L2D Slave DMA Arbitration Control Register
L2DUCARBU
L2D User Coherence Arbitration Control Resgiter
-
Reserved
L1DCPUARBD
L1D CPU Arbitration Control Register
L1DIDMAARBD
L1D IDMA Arbitration Control Register
L1DSDMAARBD
L1D Slave DMA Arbitration Control Register
L1DUCARBD
L1D User Coherence Arbitration Control Resgiter
REGISTER NAME
EMC CPU Arbitration Control Register
EMC IDMA Arbitration Control Register
C64x+ Megamodule
96
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