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| 型號(hào)： | TMX320TCI6482ZTZ |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | Communications Infrastructure Digital Signal Processor |
| 中文描述： | 通信基礎(chǔ)設(shè)施的數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 137/255頁(yè) |
| 文件大?。?/td> | 1893K |
| 代理商： | TMX320TCI6482ZTZ |
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8.7.3
PLL1 Controller Register Descriptions
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
This section provides a description of the PLL1 controller registers. For details on the operation of the PLL
controller module, see the
TMS320TCI648x DSP Software-Programmable Phase-Locked Loop (PLL)
Controller User's Guide
(literature number
SPRU806
).
NOTE:
The PLL1 controller registers can only be accessed using the CPU or the emulator.
Not all of the registers documented in the
TMS320TCI648x DSP Software-Programmable Phase-Locked
Loop (PLL) Controller User's Guide
(literature number
SPRU806
) are supported on the TMS320TCI6482.
Only those registers documented in this section are supported. Furthermore, only the bits within the
registers described here are supported. You should not write to any reserved memory location or change
the value of reserved bits.
8.7.3.1
PLL1 Control Register
The PLL control register (PLLCTL) is shown in
Figure 8-11
and described in
Table 8-19
.
31
16
Reserved
R-0
15
8
7
6
5
4
3
2
1
0
PLL
Reserved
Rsvd
Rsvd
Reserved
PLLRST
Rsvd
PLLEN
PWRDN
R-0
R/W-0
R-1
R/W-0
R/W-1
R-0
R/W-0
R/W-0
LEGEND:
R/W = Read/Write; R = Read only; -
n
= value after reset
Figure 8-11. PLL1 Control Register (PLLCTL) [Hex Address: 029A 0100]
Table 8-19. PLL1 Control Register (PLLCTL) Field Descriptions
Bit
31:8
7
6
5:4
3
Field
Reserved
Reserved
Reserved
Reserved
PLLRST
Value
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Reserved. Writes to this register must keep this bit as 0.
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
Reserved. Writes to this register must keep this bit as 0.
PLL reset bit
PLL reset is released
PLL reset is asserted
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLL power-down mode select bit
PLL is operational
PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off
PLL enable bit
Bypass mode. Divider PREDIV and PLL are bypassed. All the system clocks (SYSCLK
n
) are
divided down directly from input reference clock.
PLL mode. Divider PREDIV and PLL are not bypassed. PLL output path is enabled. All the system
clocks (SYSCLK
n
) are divided down from PLL output.
0
1
2
1
Reserved
PLLPWRDN
0
1
0
PLLEN
0
1
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C64x+ Peripheral Information and Electrical Specifications
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