參數(shù)資料
型號(hào)： TNETA1600
廠商： Texas Instruments, Inc.
英文描述： SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述： SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器）
文件頁(yè)數(shù)： 14/54頁(yè)
文件大?。?/td> 1120K
代理商： TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receive operation
The TNETA1600 receive section accepts a byte-wide data input (RPD0–RPD7) and a byte clock (RPCK) input
operating at 77.76 MHz for 622.08-Mbit/s operation or 19.44 MHz for 155.52-Mbit/s operation. The input to the
TNETA1600 must be aligned on correct byte boundaries before it is passed to the device. For example, all eight
bits of a given A1 byte must be simultaneously received on RPD0–RPD7. The TNETA1600 does not perform
a bit search to establish byte boundaries. Upon receiving the byte-wide input, a framing circuit searches for the
correct sequence of SONET/SDH framing bytes A1 and A2, where A1 has a value of F6 hex and A2 has a value
of 28 hex. The exact framing pattern for a 622.08-Mbit/s signal is twelve A1 bytes followed by twelve A2 bytes.
The framing pattern for a 155.52-Mbit/s signal is three A1 bytes followed by three A2 bytes.
The TNETA1600 provides loss-of-signal (LOS), out-of-frame (OOF), and loss-of-frame (LOF) alarms through
the controller interface in accordance with BellCore Specification GR-253-CORE, Issue 1, December 1994. The
LOS alarm goes active when no transitions are detected in the receive data for 3.2-
μ
s time period. The LOS
alarm goes inactive when two consecutive framing patterns are detected and, during the intervening time (one
frame), a lack of signal transitions for a 3.2-
μ
s time period is not detected. The OOF alarm goes active when
four consecutive erred framing patterns are received. The OOF alarm clears when two valid framing patterns
are received consecutively. If the OOF condition fails to clear within 3 ms, the LOF alarm goes active. The LOF
alarm goes inactive 1 ms after the OOF alarm clears, provided another OOF condition is not detected in that
1-ms time period. In addition to bits in the status registers, the OOF and LOF alarms are also represented by
the external pins. Setting unmasked bits in the status registers causes the INTR output of the controller interface
to go active to signal an interrupt.
The TNETA1600 provides an 8-kHz reference output (RXREF8K) that is derived from the receive-side incoming
clock signal. RXREF8K is a pulse that goes high during the period when the SONET descrambler is disabled
for the A1, A2, and C1 bytes. RXREF8K is low for the remainder of the frame. The pulse duration for the signal
is approximately 450 ns. RXREF8K is disabled (remains low) when an OOF condition is present (i.e., OOF is
high).
After the SONET/SDH frame is established, the B1 BIP-8 parity is calculated over the scrambled SONET frame.
This value is compared with the value contained in the B1 overhead location of the next frame. If the two values
do not match, the B1 parity error bit in the status register goes active, denoting that a B1 parity error has
occurred. This causes the interrupt (INTR) line to go active.
Next, the SONET/SDH frame is unscrambled, except for the A1, A2, and C1 bytes, which were not scrambled
by the transmitter. The transport-overhead bytes are copied from the SONET/SDH frame into the
receive-overhead RAM after descrambling. In addition, the data-communications and orderwire bytes are
output through the receive data-communications interface. This interface consists of a serial data output
(RSDO), a serial clock output (RCO), and a framing pulse output (RFPO). Orderwire and data-communications
bytes in a frame are internally stored until the first A1 byte of the next frame is received, at which time all 14 bytes
are continuously output in the following order: E1, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, E2. The
serial-data and framing pulse are valid on the rising edge of the RCO with the MSB of each byte clocked out
first and the least-significant bit (LSB) clocked out last. RFPO goes high to identify the concurrent output of the
MSB (first output bit) of the E1 byte. The remaining seven bits of E1 and the other13 data-communications and
orderwire bytes are then output on contiguous clock cycles. RCO is a continuous 1.215-MHz signal derived from
the receive-byte clock. However, traffic is present on the interface only about 75% of the time as there are only
14 bytes to process each frame (125
μ
s).
The B2 BIP-96 (BIP-24 for 155.52-Mbit/s operation) value is calculated over all bits of line overhead and the
envelope capacity and compared to the value contained in the next frame. If a B2 parity error occurs, the
B2-parity-error bit in the status register is set and the interrupt (INTR) line goes active to notify the controller
that a parity error has occurred.
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