參數(shù)資料
型號(hào)： TNETA1600
廠商： Texas Instruments, Inc.
英文描述： SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述： SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器）
文件頁數(shù)： 27/54頁
文件大?。?/td> 1120K
代理商： TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
disable the dropping of ATM unassigned cells from the receive-data stream
When this bit is set, the receive section does not drop ATM unassigned cells from the receive-data stream. An
unassigned cell is defined as an ATM cell with the 5-byte header set to a value of 00 00 00 00 55 (hex). When
a reset operation occurs, this bit is cleared. The normal operation of the TNETA1600 drops unassigned cells
from the receive-data stream.
enable clock looping
When this bit is set, the CLKLOOP output goes high. The CLKLOOP output on the TNETA1600 can be
connected to the CLKLOOP input on the TNETA1510/1610. When the CLKLOOP input on the
TNETA1510/1610 is active, the clock-loop function on the TNETA1510/1610 is enabled. This allows the
clock-loop function on the TNETA1510/1610 to be controlled through the controller interface on the
TNETA1600. When a reset operation occurs, this bit is cleared.
transmit the ATM unassigned cells as filler
When this bit is set, the transmit side sends ATM unassigned cells for cell-rate decoupling when a user data
cell is not available in the transmit FIFO. An unassigned cell is defined as a cell with the 5-byte header set to
a value of 00 00 00 00 55 (hex). The payload is set to all 6A (hex) bytes. When this bit is not set, the device sends
idle cells as filler cells for cell-rate decoupling. An idle cell is defined as a cell with the 5-byte header set to a
value of 00 00 00 01 52 (hex) and the payload set to all 6A (hex) bytes. When a reset operation occurs, this bit
is cleared.
place transmit-overhead RAM in program mode
This bit is logically ORed with IFPRGM. If either or both are high, the automatic write operations to transmit
overhead by the TNETA1600 are disabled. During this condition, overhead values can be written into the
TNETA1600 via the controller interface, and since these values are not automatically overwritten, this gives the
user the capability to transmit any value in any overhead-byte location. Overhead-RAM addresses that are not
written to retain their values. While in the program mode, the transmit data-communications port is disabled
(TFPO is held low). When both IFPRGM and the associated control bit are low, specified overhead bytes are
automatically overwritten each frame. Other bytes in the transmit-overhead RAM retain their programmed
values until changed manually or by a reset.
cell-interface 16-bit alternate-data format
When this bit is set, the data format for both the transmit and receive 16-bit cell interface is set to format no. 2
in Figure 3. When this bit is cleared, the data format for both the transmit and receive 16-bit cell interface is set
to format no. 1. This bit is cleared when a hardware or software reset occurs.
FORMAT NO. 1
FORMAT NO. 2
MSB Bit 15
LSB Bit 0
MSB Bit 15
LSB Bit 0
Header Byte No. 1
Header Byte No. 2
Header Byte No. 1
Header Byte No. 2
Header Byte No. 3
Header Byte No. 4
Header Byte No. 3
Header Byte No. 4
UDB No. 1
UDB No. 2
UDB No. 1
Payload Byte No. 1
Payload Byte No. 1
Payload Byte No. 2
Payload Byte No. 2
Payload Byte No. 3
:
:
:
:
:
:
:
:
Payload Byte No. 47
Payload Byte No. 48
Payload Byte No. 48
UDB No. 2
Figure 3. Cell-Interface 16-Bit Data Formats
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參數(shù)描述
TNETA1600PCM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC
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TNETA1622 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE
TNETA1622DW 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery
TNETA1630DW 制造商:Texas Instruments 功能描述:
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