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參數(shù)資料
| 型號(hào)： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器） |
| 文件頁數(shù)： | 6/54頁 |
| 文件大小： | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
transmit-cell interface
TERMINAL
NAME
I/O
DESCRIPTION
NO.
TCKI
I
Transmit clock input. Input signals are clocked into the transmit-cell interface and output signals are valid
at the transmit-cell interface on positive transitions of TCKI, when TWE is low.
TD0–TD15
I
Transmit input data. When EN155 is low (622.08-Mbit/s operation), ATM cells are clocked into the
TNETA1600 through TD0–TD15 on positive transitions of TCKI, provided TWE is low. If EN155 is high and
TWE is low (155.52-Mbit/s operation), cells are clocked in on TD0–TD7 (TD8–TD15 are not used). TD0 is
the least-significant bit.
TWE
I
Transmit write enable. A low level on TWE enables the writing of ATM cells into the transmit-cell interface.
TXCLAV
O
Transmit-cell available. TXCLAV goes high when the transmit input FIFO is capable of accepting the transfer
of a complete ATM cell. TXCLAV goes low when the TNETA1600 can accept only four more write cycles
(four bytes during 155.52-Mbit/s operation or eight bytes during 622.08-Mbit/s operation) from the
ATM-layer device without overflowing the transmit input FIFO.
TXSOC
I
Transmit start-of-cell indicator. A high level on TXSOC identifies the first byte (or first two bytes in
622.08-Mbit/s operation) of an incoming ATM cell on the transmit-cell interface. TXSOC is held low during
the remainder of that cell’s input. Once a valid TXSOC indication is detected, subsequent TXSOC
indications are ignored until the full 53 bytes of an ATM cell are received.
controller interface
TERMINAL
NAME
I/O
DESCRIPTION
NO.
A0–A10
I
Address lines. A0–A10 provide the address for accessing the internal registers and RAM. A10 is the
most-significant bit.
D0–D7
I/O
Data I/O. D0–D7 provides access to the contents of the device’s internal registers and RAM. D7 is the
most-significant bit.
INTR
O
Interrupt (open drain). INTR goes low to indicate that an unmasked condition has occurred.
RD/WR
I
Read/write control. A high-level input on RD/WR indicates a read operation and a low-level input indicates
a write operation.
READY
O
Ready. READY goes low to indicate that the device is ready to complete the requested transaction.
SEL
I
Device select. A low-level input on SEL enables the access of the device’s internal registers and RAM.
IFPRGM
I
Interface program mode. IFPRGM is logically ORed with a bit (place TX O/H RAM in program mode) in the
control register. If either or both are high, the automatic write operations to transmit overhead by the
TNETA1600 are disabled. During this condition, overhead values can be written into the TNETA1600 via
the controller interface. Since these values are not automatically overwritten, the user is given the capability
to transmit any value in any overhead-byte location. Overhead RAM addresses, which are not written to,
retain their values. While in the program mode, the transmit data-communications port is disabled (TFPO
is held low). When both IFPRGM and the associated control bit are low, specified overhead bytes are
automatically overwritten each frame after the first row’s overhead has been transmitted.
LOPC
I
Loss of optical carrier. When LOPC goes high, a bit is set in the status register, and if not masked, an interrupt
is generated on INTR. This provides an interrupt through the controller interface to the host indicating that
the incoming optical signal has been lost. When LOPC goes low, the bit in the status register goes low and
an interrupt is (again) generated on INTR.
CLKLOOP
O
Clock loopback. CLKLOOP is at a high level when the corresponding bit in the control register is at a high
level. Similarly, if the control register bit is low, CLKLOOP is low. This allows a clock-loopback function on
a line-side device (i.e., a TNETA1510, TNETA1610, or TNETA1611) to be controlled through the controller
interface of the TNETA1600.
FLB
O
Facility loopback. FLB is at a high level when the corresponding bit in the control register is at a high level.
Similarly, if the control register bit is low, FLB is low. This allows a facility-loopback function on a line-side
device (i.e., a TNETA1510, TNETA1610, or TNETA1611) to be controlled through the controller interface
of the TNETA1600.
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時(shí)鐘發(fā)生裝置) |
| TO-252 | TO-252 (MP-3Z) |
| TODX2402 | FIBER OPTIC TRANSCEIVING MODULE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TNETA1600PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC |
| TNETA1611PCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver |
| TNETA1622 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE |
| TNETA1622DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery |
| TNETA1630DW | 制造商:Texas Instruments 功能描述: |
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