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參數(shù)資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機(jī)接收器/傳送器） |
| 文件頁數(shù)： | 41/54頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
41
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
IDCODE
The IDCODE instruction connects the device-identification register in the scan path for serial access in the
Shift-DR state. For the TNETA1600, the identification code is 0003202F (hex). The device operates in the
normal mode.
SAMPLE/PRELOAD
The sample/preload instruction provides a sampling method for examining device inputs and outputs without
interfering with the normal operation of the system logic in the device. The boundary-scan register is selected
in the scan path. The TNETA1600 inputs and outputs are captured by loading the boundary-scan register in the
Capture-DR state. These values are output by shifting the register through TDO in the Shift-DR state. This
instruction also includes a preload function that allows a desired data pattern to be placed at the outputs of the
boundary-scan register cells. The device operates in the normal mode.
BYPASS
This instruction allows system-level test data to be quickly passed through the TNETA1600 with a single
clock-period delay. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass
register during the Capture-DR state. The device operates in the normal mode.
HIGHZ
This instruction is used to place the TNETA1600 into a modified test mode in which all device output pins are
placed in the high-impedance state. The bypass register is selected in the scan path. A logic 0 value is captured
in the bypass register during the Capture-DR state. Device input pins remain operational, and the normal
on-chip logic is exercised.
CLAMP
The CLAMP instruction allows device outputs to be set and held at a desired state. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during the Capture-DR state. When
the CLAMP instruction is selected, outputs are defined by data held in the boundary-scan register. These
outputs do not change as long as the CLAMP instruction is selected. Device input pins remain operational, and
the normal on-chip logic is exercised. The device operates in the test mode.
CELLTST
This instruction connects the boundary-scan register in the scan path. All boundary-scan cells capture the
inverse of their current values during the Capture-DR state. In this way, the contents of the shadow latches can
be read out to verify the integrity of both shift-register and shadow-latch elements of the boundary-scan register.
The device operates in normal mode.
bypass register
The bypass register is a 1-bit scan path offering a single-bit delay from TDI to TDO. This register can be selected
in the device scan path to shorten the length of the system scan path, reducing the number of bits per test pattern
that must be applied to complete a test operation. During the Capture-DR state, the bypass register captures
a logic 0.
device-identification register
The device-identification register is 32 bits long. It can be selected and read to identify the manufacturer, part
number, and version of this device. For the TNETA1600, the binary value (MSB to LSB) 0000 0000 0000 0011
0010 0000 0010 1111 (0003202F hex) is captured during the Capture-DR state in the device-identification
register to identify the device as Texas Instruments TNETA1600. The device-identification register order of scan
is from TDI through bits 31–0 to TDO.
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| TNETA1600PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC |
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| TNETA1622DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery |
| TNETA1630DW | 制造商:Texas Instruments 功能描述: |
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