參數(shù)資料
型號(hào)： TNETA1600
廠商： Texas Instruments, Inc.
英文描述： SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器)
中文描述： SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器）
文件頁數(shù)： 42/54頁
文件大?。?/td> 1120K
代理商： TNETA1600
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
42
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundry-scan register
The boundary-scan register forces values on device-output terminals and/or captures data that appears at the
inputs and/or outputs of the normal on-chip logic. The source of data to be captured into the boundary-scan
register during the Capture-DR state is determined by the current instruction. While in the Test-Logic-Reset
state, each bit in the boundary-scan register is reset to logic 0 except bits TBD which are reset to logic 1. The
boundary-scan register order of scan is from TDI, through bits 109–0, to TDO. Table 12 shows the
boundary-scan register bits and their associated device-pin signals.
pointer-processing test functionality
The TAP interface accesses pointer-processing circuitry for a more efficient manufacturing test and a more
comprehensive fault coverage on certain portions of this circuitry. The following paragraphs are primarily
intended for use by the manufacturer.
This special test functionality tests circuitry for the address generation and comparison of all valid J1 pointer
locations, as well as the path-overhead column locations. The synchronous payload envelope-counter
operation and x-column position counter operation are also verified. Algorithms used to check the validity of
pointer addressing, identifying NDF, LOP and other pointer-processing functions are not verified in this test
mode.
When placed into this test mode, the circuitry is first reset and placed into the decrement mode beginning at
J1 = 0. Each pulse of the test clock then increments the SPE counter, while every third clock decrements the
J1-pointer value. For STS-3c, only every third SPE location is used for J1. No comparison is performed during
this time, since the address values are running in the opposite direction from the SPE values. However, the
decrements must happen properly or the remainder of the test procedure fails. After a specified number of test
clock cycles, J1 is decremented through the entire range of values returning to J1 = 0.
Next, the circuitry must be placed into the increment mode and incremented through the J1 range. During this
phase, the SPE counter and incremented addresses are compared. This should result in a matched signal on
every third position. This matched signal is scanned into a signature register and also used as feedback to
control the clock signal. Any failure on this comparison causes the SPE counter and address increment to get
out of step, resulting in no further matches for the remainder of the test. At the end of this procedure if all J1
values are valid, a test result signature is scanned out, verifying the test results.
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相關(guān)PDF資料
PDF描述
TNETA1610 STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器)
TNETA1611 STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器)
TNETA1630 622.08-MHz Clock-Recovery Device(622.08-MHz時(shí)鐘發(fā)生裝置)
TO-252 TO-252 (MP-3Z)
TODX2402 FIBER OPTIC TRANSCEIVING MODULE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TNETA1600PCM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC
TNETA1611PCA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver
TNETA1622 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE
TNETA1622DW 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery
TNETA1630DW 制造商:Texas Instruments 功能描述:
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