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參數資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發(fā)送器為622.08，麻省理工學院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數： | 30/54頁 |
| 文件大小： | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
force-transmit path RDI -11
When set to a high level, this bit forces the transmission of a 1 in bit 5 and a 1 in bit 6 of the transmit G1 byte.
When this bit is low, normal processing occurs such that the value inserted in bits 5 and 6 of the G1 byte follows,
provided that they are not otherwise altered through the controller interface. When a reset operation is
performed, this bit is cleared (set to 0).
enable SDH frames
The bit is logically ORed with the SDHEN terminal. SDH frames are processed if this bit is set to a high level,
if SDHEN is high, or if both are high. SONET frames are processed only if both SDHEN and this bit are low. To
change the framing mode, a valid clock must be present on TPCK as new values are written to the
transmit-overhead RAM. The transmit-framing functions are reset when the SONET/SDN mode is changed.
Transmit-frame alignment may be lost, along with any data being processed in the transmit circuitry. When a
hardware or software reset occurs, this bit is cleared (set to 0) and new values are written to overhead. These
new overhead values are SONET values if SDHEN is low. If SDHEN is high, these new overhead values are
SDH values.
ID register
The ID register is located at address 006 (hex). The register identifies the chip revision. It also provides a means
of performing a software reset. The contents of this register are hardwired to a hexadecimal value of 5x (binary
0101 XXXX), where x (XXXX) denotes the chip revision. A software reset on the TNETA1600 device can be
initiated by performing a write to the ID register through the controller interface. Since the contents of the ID
register are hardwired, the write does not change the contents of the register. The software-reset function is
logically ORed with the RESET input, so a reset of the TNETA1600 device can be initiated by taking the external
pin low or by writing to the ID register. Because default SONET or SDH values are written to the overhead RAM,
a valid clock must be present at TPCK when a software reset is executed. Similarly, a valid clock must be
available to TPCK when the hardware-reset signal (on the RESET terminal) transitions from the low state back
to the high (normal) state. For example, if operating the TNETA1600 with the TNETA1610, a common
hardware-reset signal sent to each device’s RESET terminal must remain low for at least TBD ms to ensure that
the TNETA1610 TPCK clock output (to the TNETA1600) is valid when the RESET terminal returns high.
consecutive-event counts
The TNETA1600 contains several frame counters that provide a way to program the number of consecutive
frames required to activate and deactivate alarms in the status registers. Table 7 lists the registers available
through the TNETA1600 controller interface for such programmability. All registers have eight bits.
Table 7. Event Consecutive-Frame Counts
ADDRESS
(HEX VALUE)
016
REGISTER
Line-AIS consecutive-frame count
017
Line-FERF consecutive-frame count
018
Line-RDI consecutive-frame count
019
LOCA to path-RDI soak count
line-AIS consecutive-frame count
A line-AIS condition is detected in a frame as a 111 in bits 6–8 of the K2 byte. Any other pattern is not an LAIS
pattern. The input to this register represents the number of consecutive frames in which the condition must occur
for activation and, independently, the required number of consecutive frames without the condition for
deactivation of the LAIS bit in status register 2. As activation (and deactivation) may occur upon the detection
of the condition for up to 15 consecutive frames, the four most-significant bits of the register are used to
represent the number of consecutive frames (with the condition) required for activation while the four
least-significant bits represent the number of consecutive frames (without the condition) required for
deactivation. For example, to activate an interrupt through the status registers upon the detection of a condition
P
相關PDF資料 |
PDF描述 |
|---|---|
| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時鐘發(fā)生裝置) |
| TO-252 | TO-252 (MP-3Z) |
| TODX2402 | FIBER OPTIC TRANSCEIVING MODULE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TNETA1600PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC |
| TNETA1611PCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver |
| TNETA1622 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE |
| TNETA1622DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery |
| TNETA1630DW | 制造商:Texas Instruments 功能描述: |
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