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參數資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發(fā)送器為622.08，麻省理工學院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數： | 15/54頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receive operation (continued)
The location of the J1 byte in the SPE must be determined from the H1 and H2 bytes in the transport overhead.
The location of the J1 byte does not change from the previous frame unless the first four bits of H1 are set to
1001 (the new-data flag) or the pointer value contained in H1 and H2 is different for three consecutive frames.
The location of J1 also can be incremented or decremented one byte slot by inverting certain bits in the H1 and
H2 byte pointer. If at least three of the five bits 7, 9, 11, 13, and 15 are inverted, the location of J1 is incremented
one slot. If at least three of the five bits 8, 10, 12, 14, and 16 are inverted, the location of J1 is decremented one
slot. Subsequent pointers contain the new offset.
The TNETA1600 provides a loss-of-pointer (LOP) alarm in the controller interface to indicate that either an
invalid pointer is detected for eight consecutive frames in the incoming H1 and H2 bytes or a new-data flag (NDF)
that is set to a value of 1001 (the first four bits of H1) is found in eight consecutive frames. The LOP alarm goes
inactive when a valid pointer (with the NDF set to 0110) is detected in three consecutive frames. The
TNETA1600 provides a PAIS alarm in the controller interface to indicate that a path PAIS condition is detected
in the H1 and H2 bytes. A PAIS condition is detected as an all ones condition in bytes H1 and H2 for three
consecutive frames. The PAIS alarm goes inactive when a valid, identical pointer (with the NDF set to 0110)
is detected for three consecutive frames or when a valid pointer is observed with NDF set to 1001. The LOP
alarm is not set if a PAIS condition is detected. Decoding of the NDF is performed by majority voting (i.e., the
NDF is detected as being set if three or four of the bits match the 1001 code).
The TNETA1600 evaluates the incoming receive transport- and path-overhead bytes for error reporting from
the transmitting system. The TNETA1600 checks for a LAIS, LFERF, PFERF, and PRDI. The LAIS alarm is
activated when bits 6–8 of the incoming K2 byte are set 111 for five
consecutive frames. The LAIS alarm is
deactivated when bits 6–8 of K2 byte are set to any pattern other than 111 for five
consecutive frames. The
LFERF alarm is activated when bits 6–8 of K2 byte are set to 110 for five
consecutive frames. The LFERF alarm
is deactivated when bits 6–8 of the K2 byte are set to any pattern other than 110 for five
consecutive frames.
The path FERF alarm is activated when bits 1–4 of the G1 byte are set to 1001. The path PRDI alarm is activated
when bit 5 or bit 6 (or both) of the G1 byte is set to 1 for ten
consecutive frames. The PRDI alarm is deactivated
when bits 5 and 6 of the G1 byte are set to 00 for ten
consecutive frames or when a PAIS defect is detected
on the affected path.
The B3 BIP-8 byte is calculated over the contents of the SPE, which begins with the J1 byte. The value
calculated for B3 is compared with the value found in the next frame. If a B3 parity error occurs, the B3 parity
error bit is set in the status register and INTR goes active to notify the external controller.
Cumulative counts of receive B1, B2 and B3 errors are provided by counters accessible through the controller
interface. Running totals of both B1, B2, and B3 block errors and coding violating are maintained. The
block-error counters maintain a count of the number of frames that are received with B1, B2, and B3 errors. The
coding-violation counters count the exact number of B1, B2, and B3 bit-interleaved parity (BIP) errors that occur.
The TNETA1600 also provides counters that accumulate the line-far-end and path-far-end block errors reported
by the incoming Z2 and G1 bytes. When any of these counters reach maximum count, a bit is set in the status
registers and an interrupt is generated. These counters are all rollover counters (i.e., they roll over to zero after
the maximum count occurs and an interrupt is generated).
Once the SPE is located, the TNETA1600 extracts the path-overhead bytes and stores them in the receive
overhead RAM. The TNETA1600 provides for the storage of 64 consecutive J1 bytes, allowing an external
device to read the last 64 bytes received in the J1 position and check for the proper path trace. The TNETA1600
checks the C2 byte to determine if signal-label mismatch has occurred. Two signal-label-mismatch conditions
are monitored via the C2 byte. A path-unequipped defect is indicated when C2 = 00 (hex) for five consecutive
frames, while a payload-label-mismatch defect is indicated when C2 is any value other than 00, 01, or 13 (hex)
for five consecutive frames. Each defect is independently represented by a bit in the status register.
The number of frames in which an event must occur to activate or deactivate the LAIS, LFERF, and PRDI signals is programmable for each signal,
independently, via the control registers. Default values are shown in the above text but can be changed to any whole number between one and
fifteen.
P
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