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| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數(shù)： | 17/54頁 |
| 文件大?。?/td> | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receive operation (continued)
The data output on the receive-cell interface is 16 bits wide for 622.08-Mbit/s operation and 8 bits wide for
155.52-Mbit/s operation. The width of the datapath is set when the user chooses either 155.52- or 622.08-Mbit/s
operation through the EN155 input. For the 16-bit data output, the TNETA1600 is configured to transfer data
in two different formats. For the first format, data is output as 54 bytes per ATM cell with two user-defined bytes
(UDBs) separating the four bytes of the ATM header from the cell payload. The second format has one UDB
separating the four bytes of the ATM header from the cell payload and a second UDB at the end of the cell
payload. These two formats are shown in Figure 2. The selection of the data format is made via the control
register that is accessible through the controller interface. When a hardware or software reset occurs, the
TNETA1600 is set up to output data using format no. 1. In each format, the second UDB is an all-zeroes pattern.
For the 8-bit data interface, data is output as a 53-byte ATM cell with one UDB separating the four bytes of the
ATM header from the 48-byte cell payload.
FORMAT NO. 1
FORMAT NO. 2
MSB Bit 15
LSB Bit 0
MSB Bit 15
LSB Bit 0
Header Byte No. 1
Header Byte No. 2
Header Byte No. 1
Header Byte No. 2
Header Byte No. 3
Header Byte No. 4
Header Byte No. 3
Header Byte No. 4
UDB No. 1
UDB No. 2
UDB No. 1
Payload Byte No. 1
Payload Byte No. 1
Payload Byte No. 2
Payload Byte No. 2
Payload Byte No. 3
:
:
:
:
:
:
:
:
Payload Byte No. 47
Payload Byte No. 48
Payload Byte No. 48
UDB No. 2
Figure 2. Receive Cell-Interface Formats for 16-Bit Output Data
When the receive side enters a LOCA state, a PRDI can be sent out the transmit side through the outgoing G1
byte. If enabled through a bit in the control registers, a PRDI is transmitted when a LOCA state is persistent for
an amount of time (known as soak time) that has not yet been specified by any of the standards organizations.
To provide maximum flexibility to this unspecified soak time, an 8-bit counter is provided through the controller
interface that allows the user to program soak time for a PRDI alarm in increments of 125
μ
s. This counter is
preset to a value of 4 ms when a device reset occurs.
controller interface
The controller interface provides access to the internal memory locations that contain the control registers,
status registers, interrupt-mask registers, ID register, receive- and transmit-overhead registers, and
performance counters. The controller interface consists of eight data (D0–D7) I/O pins, eleven address
(A0–A10) input pins, a SEL input, a RD/WR input, a READY output, and an open-drain INTR output. The
interface also provides an IFPRGM input that, along with a bit in the control register, can be used to place the
device in the program mode. While in the program mode, transmit-overhead values (i.e., parity bytes) are not
automatically updated by the TNETA1600.
Table 2 shows a memory map of the TNETA1600 controller interface, broken into the four major areas. This map
is valid for both 155.52- and 622.08-Mbit/s operation.
Table 2. TNETA1600 Memory Map
MEMORY BLOCK
BEGINNING
ADDRESS
(HEX)
Control and status registers
000
Performance counters
100
Receive-overhead bytes
200
Transmit-overhead bytes
400
P
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