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參數(shù)資料
| 型號： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動柜員機接收器/發(fā)送器為622.08，麻省理工學院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動柜員機接收器/傳送器） |
| 文件頁數(shù)： | 23/54頁 |
| 文件大小： | 1120K |
| 代理商： | TNETA1600 |
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TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
path FEBE-counter overflow
This status bit indicates that the path FEBE counter has rolled over because of counter overflow. The INTR
output goes active and this bit is set when the counter overflows.
output ATM-cell-counter overflow
This status bit indicates that the output
ATM-cell counter has rolled over because of counter overflow. The INTR
output goes active and this bit is set when the counter overflows.
discarded-idle/unassigned-cell-counter overflow
This status bit indicates that the discarded-idle/unassigned-cell counter has rolled over because of counter
overflow. The INTR output goes active and this bit is set when the counter overflows.
single-bit-error ATM-cell-counter overflow
This status bit indicates that the single-bit-error ATM-cell counter has rolled over because of counter overflow.
The INTR output goes active and this bit is set when the counter overflows.
multiple-bit-error ATM-cell-counter overflow
This status bit indicates that the multiple-bit-error ATM-cell counter has rolled over because of counter overflow.
The INTR output goes active and this bit is set when the counter overflows.
payload-label mismatch
This bit is set when a C2 byte is received that contains a value other than 00, 01, or 13 hex for five consecutive
frames, provided a PAIS or LOP condition is not detected on the incoming signal. The bit is cleared when the
C2 byte is received that contains 01 hex (indicating equipped nonspecific) or 13 hex (indicating mapping for
ATM) for five consecutive frames or when a path-unequipped PAIS or LOP defect is detected. A hardware or
software reset causes this bit to clear. This bit is set as long as the mismatch condition exists. When the logic
in the TNETA1600 detects that the mismatch has cleared, the status bit in the status register is cleared. A
change in the bit causes the INTR output to go active. When the status bit makes a low-to-high transition, the
INTR output goes active. The INTR output also goes active when the status bit makes a high-to-low transition.
Reading the status register does not clear the status bit for this alarm. However, the INTR output goes inactive
on a read of any of the status registers.
path unequipped
This bit is set when the C2 byte contains a value of 00 hex in five consecutive frames, provided a PAIS or LOP
is not detected on the incoming signal. The bit is cleared when the C2 byte contains any value other than
00 hex for five consecutive frames or when a PAIS or LOP is detected. A hardware or software reset causes
this bit to be cleared. This bit is set as long as the condition exists. When the logic in the TNETA1600 detects
that the condition has cleared, the status bit in the status register is cleared. A change in the bit causes the INTR
output to go active. When the status bit makes a low-to-high transition, the INTR output goes active. The INTR
output also goes active when the status bit makes a high-to-low transition. Reading the status register does not
clear the status bit for this alarm. However, the INTR output goes inactive on a read of any of the status registers.
P
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TNETA1600PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC |
| TNETA1611PCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver |
| TNETA1622 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE |
| TNETA1622DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery |
| TNETA1630DW | 制造商:Texas Instruments 功能描述: |
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