- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385942 > TNETA1600 (Texas Instruments, Inc.) SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) PDF資料下載
參數(shù)資料
| 型號(hào)： | TNETA1600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET/SDH ATM Receiver/Transmitter for 622.08-Mit/s or 155.52-Mbit/s Operation(SONET/SDH ATM接收器/傳送器) |
| 中文描述： | SONET / SDH的自動(dòng)柜員機(jī)接收器/發(fā)送器為622.08，麻省理工學(xué)院/ s或155.52 - Mbit / s的操作（SONET / SDH的自動(dòng)柜員機(jī)接收器/傳送器） |
| 文件頁數(shù)： | 52/54頁 |
| 文件大小： | 1120K |
| 代理商： | TNETA1600 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當(dāng)前第52頁第53頁第54頁
TNETA1600
SONET/SDH ATM RECEIVER/TRANSMITTER
FOR 622.08-MBIT/S OR 155.52-MBIT/S OPERATION
SDNS036 – FEBRUARY 1996
52
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements (see Figure 12)
NO.
MIN
MAX
UNIT
1
tsu(RD/WR)
Setup time, RD/WR low before SEL
↓
ns
2
tsu(A0–A10)
Setup time, A0–A10 valid before SEL
↓
ns
3
tsu(D0–D7)
Setup time, D0–D7 valid before SEL
↓
ns
4
th(D0–D7)
Hold time, D0–D7 valid after SEL
↓
ns
5
th(A0–A10)
th(SEL)
th(RD/WR)
Hold time, A0–A10 valid after SEL
↓
ns
6
Hold time, SEL low after READY
↓
ns
7
Hold time, RD/WR low after SEL
↑
ns
operating characteristics (see Figure 12)
NO.
PARAMETER
MIN
MAX
UNIT
8
td(READY)1
Delay time, SEL
↓
to READY
↓
ns
9
td(READY)2
Delay time, SEL
↑
to READY
↑
ns
When accessing status registers, interrupt-mask registers, control registers, counters, etc. (addresses 000–1FF), the maximum delay (SEL
↓
to READY
↓
) is to be determined (TBD) in nanoseconds. However, when accessing overhead RAM (addresses 200–5FF), the negative transition
of READY in response to SEL may be delayed by internal usage of the overhead RAM. In this case, the maximum possible delay is TBD in
microseconds.
RD/WR
(input)
SEL
(input)
1
2
3
7
A0–A10
(input)
8
D0–D7
(input)
6
9
5
4
READY
(output)
Figure 12. Controller-Interface Write Cycle
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TNETA1610 | STS-12c/STM-4 Receiver/Transmitter with Clock Recovery/Generation(STS-12C/STM-4接收/傳送器) |
| TNETA1611 | STS-12c/STM-4 Receiver/Transimitter(STS-12C/STM-4接收/傳送器) |
| TNETA1630 | 622.08-MHz Clock-Recovery Device(622.08-MHz時(shí)鐘發(fā)生裝置) |
| TO-252 | TO-252 (MP-3Z) |
| TODX2402 | FIBER OPTIC TRANSCEIVING MODULE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TNETA1600PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET FRAMER|QFP|160PIN|PLASTIC |
| TNETA1611PCA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Transceiver |
| TNETA1622 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:622.08-MHz CLOCK-RECOVERY DEVICE |
| TNETA1622DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock/Data Recovery |
| TNETA1630DW | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。